Abstract: A memory device includes an address decoder, a global data line, and a plurality of memory blocks, which are each coupled to the address decoder and the global data line. Each memory block includes a plurality of column lines, a local data line, and a plurality of memory cells that are arranged in columns and are each coupled to a corresponding one of the column lines. Each memory block also includes or has associated therewith a switching circuit that is coupled to the column lines and the local data line. The switching circuit couples a selected column line to the local data line and couples the local data line to the global data line when the memory block is selected. The switching circuit uncouples each of the column lines from the local data line when the memory block is unselected, or during a read cycle when the memory block is selected and the sense-amplifier is enabled.

Abstract: A write global bus driver is provided within the data input buffer. The write global bus driver has the same circuit configuration as the read global bus driver so that it drives the output buffer with the very same type of signal and in the same way as the read global bus driver drives the output buffer. The write global bus driver is coupled to the global data bus for placing written data on the global data bus that is normally used only for read data. During each write cycle, the data is written simultaneously to the memory array and to the output buffer. The output buffer is a two-stage, pipelined output buffer. When data is stored in the first stage of the output buffer, whether write data or read data, it is maintained in the first stage on the same clock cycle that it is presented. On the subsequent clock cycle, the data from the first stage is transferred to the second stage and is provided as the output of the output buffer.

Abstract: A bias circuit for generating a bias voltage over variations in the power supply voltage and over process parameters is disclosed. The bias circuit utilizes a voltage divider to generate a divided voltage based on the power supply value. The divided voltage is applied to the gate of a modulating transistor (biased in saturation) in a current mirror, which controls a current applied to a linear load device biased in the linear region. The voltage across the load device determines the bias voltage. Variations in the power supply voltage are thus reflected in the bias voltage, such that the gate-to-source voltage of the series transistor is constant over variations in power supply voltage. Variations in process parameters that produce different transistor current drive characteristics are reflected in a variations of the bias voltage produced by the linear load device.

Abstract: A bias circuit for generating a bias voltage that tracks power supply voltage variations, and that is compensated for variations in p-channel transistor and process parameters, is disclosed. The bias circuit includes a voltage divider, such as a resistor divider, that produces a ratioed voltage based on the power supply voltage to be tracked. The ratioed voltage is applied to a first input of a differential stage, the output of which is applied to an intermediate stage including a drive transistor and a load; the second input of the differential stage receives a feedback voltage from an intermediate node that is connected to the source of a p-channel modulating transistor that has its gate biased so as to be in saturation, for example at ground. The current conducted by the p-channel modulating transistor depends upon the ratioed voltage from the voltage divider, and also on its transistor characteristics.

Abstract: According to the present invention, a structure and method provides for single bit failures of an integrated circuit memory device to be analyzed. According to the method for analyzing a single bit failure of an integrated circuit memory device, a test mode is entered, bitline load devices of the integrated circuit memory device are turned off, a single bit of the integrated circuit memory device is selected, the device is placed into a write mode, a plurality of bitlines true and a plurality of bitlines complement of the integrated circuit memory device not associated with the single bit are then set to a low logic level, the bitline true and the bitline complement associated with the single bit is connected to a supply bus and a supply complement bus which is connected to test pads. Finally, the electrical characteristics of the single bit can be monitored on the test pads.

Abstract: An input buffer, for an asynchronous integrated memory circuit incorporating a memory circuit, including a latch circuit controlled by a write enable signal is disclosed. The input stage of the input buffer is connected to a pass gate, which is controlled by the write enable signal so that the pass gate is nonconductive when the write enable signal is active. The output of the pass gate is connected to an input of the latch circuit. The latch circuit is controlled by the write enable signal so that the signal present on the input of the latch is latched when the write enable signal is active. From an output of the latch circuit are obtained true and complementary signals, which are applied to outputs of the buffer circuit. As a result, when the write enable signal is active, the signal present on the input of the buffer is latched and presented to the outputs of the buffer, and the latch circuit is isolated from the input of the buffer until the write cycle is terminated.

Abstract: Circuitry for performing a special test of an integrated memory circuit is disclosed, where the special test requires driving of both bitlines associated with a column of memory cells to a selected logic level, such as ground. The special test is performed in a mode different from normal operation of the memory, and is useful in performing a write disturb test, and in performing stress tests of memory elements such as pass transistors in static random access memory cells. The special test is performed by generating an internal signal selecting the placement of both bitlines in one or more bitline pairs to the selected logic level. Circuitry is also disclosed which uses the output enable terminal, in the special test mode, for controlling the driving of both bitlines to the selected logic level, as the output enable terminal otherwise has no required function in this special test mode.

Abstract: According to the method of the present invention, stress testing of decoders and other periphery circuits of synchronous RAMs is performed within a reasonable period of time and without an increase in the complexity of stress testing or fabrication of synchronous RAMs. In order to stress test decoders and periphery circuits of a synchronous RAM to obtain maximum fault coverage of possible latent defects, a periphery stress mode is defined through appropriate manipulation of the Power-On Reset signal of the device such that all nodes of a memory array of the synchronous RAM are pulled in the opposite logic state from that required for a memory cell stress mode. In the periphery stress mode, the Power-On Reset signal is allowed to pulse upon power-up of the synchronous RAM device such that latches and flip flops of the device are forced in a logic state that disables all rows and columns of the memory array of the device. Additionally, all D.C.

Abstract: A method and circuit for significantly reducing a delay added to a clock signal which clocks an output of a first circuit into an input of a second circuit in a semiconductor device. An output of a first circuit is connected to a data line. The first circuit is designed with elements having a selected set of design parameters, such as transistor dimensions and transistor orientation. A second circuit is connected to the data line and also receives a clock signal generated by a signal delay circuit. The signal delay circuit receives an output enable signal, and after a delay period, produces the clock signal in response to the output enable signal. At least a portion of the signal delay circuit utilizes elements having the selected set of design parameters utilized in the first circuit.

Abstract: An integrated circuit with an integer odd number C of electrical contacts, wherein each of the electrical contacts is for communicating a data value. The integrated circuit also includes four memory arrays for storing data. The first and third memory arrays are operable to simultaneously output an integer even number E of data values. The second and fourth memory arrays are operable to simultaneously output an integer odd number D of data values. The integrated circuit further includes circuitry for selectively coupling the first, second, third, and fourth memory arrays to the electrical contacts, wherein the circuitry for selectively coupling is operable to couple the first and fourth memory arrays to the electrical contacts in a first state so that the first memory array outputs E data values and the fourth memory array outputs D data values in the first state.

Abstract: A circuit and related method are provided for parallel stressing of a plurality of memory circuits integrated on dies on a silicon wafer. On each die, a test mode control circuit, having a first and a second test mode control inputs, and a test enable circuit, having a first and a second test enable inputs, are used to enable test operation mode and to force outputs of address buffers, data buffers and other signal buffers, like chip-enable or write buffers, to predetermined logic values so that all row and column decoders are selected and predetermined data is written into the memory cells. Contemporaneously are also exercised entire paths of buffers. The silicon wafer is then heated and maintained at an elevated temperature for a desired time, and then cooled down. In this way it is possible to stress test for ionic contamination, trap sites and weak oxides a plurality of integrated circuits on the same wafer in a short time, requiring only a limited number of test signals.

Abstract: A read circuit for a memory cell includes a sense amplifier and an equilibrate circuit. The sense amplifier is coupled to the memory cell via a pair of data lines, and amplifies the data signals that the memory cell provides. The equilibrate circuit is coupled to the sense amplifier, receives an equilibrate signal, and, when the equilibrate signal has an active level, equilibrates the sense amplifier. When the equilibrate signal has an inactive level, the equilibrate circuit causes the sense amplifier to draw substantially zero supply current, regardless of the levels of any signals on the data lines. The read circuit may also include an enable circuit that receives an enable signal and is coupled to the sense amplifier. When the enable signal has an active level, the enable circuit allows the sense amplifier to amplify the data signals on the data lines. When the enable signal has an inactive level, the enable circuit prohibits the sense amplifier from amplifying the data signals on the data lines.

Abstract: The time required to output data from an output buffer is significantly reduced by having a slave latch in a parallel connection with a master latch. Incoming data is stored in a master latch on a first phase of a clock pulse. On the second phase of the clock pulse, the data is output of the master latch and provided to an output driver. A slave latch is coupled to the input node of the output driver. On the subsequent phase of the clock, the slave latch is switched on to hold the state of the input to the output driver constant. The slave latch thus receives the output of the master register in parallel with the output driver and also performs its function of maintaining the input to the output buffer for one entire clock pulse while new data is being presented to the master latch. Data is thus provided more quickly to the output driver than was previously possible with prior art master/slave configurations.

Abstract: A redundancy structure having fewer pass gates in the redundant decoder for quicker access to a redundant columns and a reduction in the complexity of the redundancy structure.

Abstract: A plurality of bit lines is arranged in columns and grouped into a first set of bit lines and a second set of bit lines. Each bit line in the first set of bit lines alternates with each bit line in the second set of bit lines. First switching means electrically connects the first set of bit lines to a first voltage level and, simultaneously, second switching means connects the second set of bit lines to a second voltage level. This permits a bit line stress test that will reveal defects or failures in a memory chip.

Abstract: An output driver circuit for an integrated circuit is disclosed, where the output driver drives an output terminal with a high logic level having a voltage limited from the power supply voltage of the integrated circuit. The limited voltage is provided by applying a limited output high voltage to an output buffer, such that the drive signal applied to the gate of the pull-up transistor in the output driver is limited by the limited output high voltage applied to the output buffer. A voltage reference and regulator circuit for generating the limited output high voltage is also disclosed, and is based on a current mirror. The sum of the current in the current mirror is controlled by a bias current source, which may be dynamically controlled within the operating cycle or programmed by way of fuses.

Abstract: An output driver circuit for an integrated circuit is disclosed, where the output driver drives an output terminal with a high logic level having a voltage limited from the power supply voltage of the integrated circuit. The limited voltage is provided by applying a limited output high voltage to an output buffer, such that the drive signal applied to the gate of the pull-up transistor in the output driver is limited by the limited output high voltage applied to the output buffer. A voltage reference and regulator circuit for generating the limited output high voltage is also disclosed, and is based on a current mirror. The sum of the current in the current mirror is controlled by a bias current source, which may be dynamically controlled within the operating cycle or programmed by way of fuses.

Abstract: An output driver circuit for an integrated circuit is disclosed, where the output driver drives an output terminal with a high logic level having a voltage limited from the power supply voltage of the integrated circuit. The limited voltage is provided by applying a limited output high voltage to an output buffer, such that the drive signal applied to the gate of the pull-up transistor in the output driver is limited by the limited output high voltage applied to the output buffer. A voltage reference and regulator circuit for generating the limited output high voltage is also disclosed, and is based on a current mirror. The sum of the current in the current mirror is controlled by a bias current source, which may be dynamically controlled within the operating cycle or programmed by way of fuses.

Abstract: A circuit and related method are provided internally to an integrated circuit for stress testing its memory. A test mode control circuit, having a first and a second test mode control input, is used, during special test operation mode, to force outputs of address buffers, data buffers and other signal buffers, like chip-enable or write buffers, to predetermined logic values so that all row and column decoders are selected and predetermined data is written into the array of memory cells. Contemporaneously are also exercised entire paths of buffers. The integrated circuit is heated and maintained at an elevated temperature for a desired time, and then cooled down. In this way it is possible, at wafer level, to stress test for ionic contamination, trap sites and weak oxides the integrated circuit in a short time, requiring only a limited number of test signals.

Abstract: A dual-port data cache is provided having one port dedicated to servicing a local processor and a second port dedicated to servicing a system. The dual-port data cache is also capable of a high speed transfer of a line or lines of entries by placing the dual-port data cache in "burst mode." Burst mode may be utilized with either a read or a write operation. An initial address is latched internally, and a word line in the memory array is activated during the entire data transfer. A control circuit is utilized to cycle through and access a number of column addresses without having to provide a separate address for each operation.