Abstract: Techniques are provided for radio frequency interconnections between oscillators and transmission lines for oscillatory neural networks (ONNs). An ONN gate implementing the techniques according to an embodiment includes a transmission line, a first oscillator circuit tuned to a first frequency based on a first tuning voltage associated with a first synapse weight, and a first capacitive coupler to couple the first oscillator circuit to the transmission line to generate an oscillating signal in the transmission line. The ONN gate further includes a second oscillator circuit tuned to a second frequency based on a second tuning voltage associated with a second synapse weight, and a second capacitive coupler to couple the second oscillator circuit to the transmission line to adjust the oscillating signal in the transmission line such that the amplitude of the adjusted oscillating signal is associated with a degree of match between the first frequency and the second frequency.

Abstract: An apparatus is provided which comprises: a stack comprising a magnetoelectric (ME such as BiFeO3, (LaBi)FeO3, LuFeO3, PMN-PT, PZT, AlN, SmBiFeO3, Cr2O3, etc.) material and a transition metal dichalcogenide (TMD such as MoS2, MoSe2, WS2, WSe2, PtS2, PtSe2, WTe2, MoTe2, graphene, etc.); a magnet adjacent to a first portion of the TMD of the stack; a first interconnect adjacent to the magnet; a second interconnect adjacent to the ME material of the stack; and a third interconnect adjacent to a second portion of the TMD of the stack.

Abstract: A neural network scheme is described that uses unsupervised learning in oscillator neural networks. Training occurs by varying the weights in proportion to the output from a frequency detector. Inputs and initial weights are split into plurality of inputs and plurality of weights. These split inputs and weights can be analog or digital. Oscillators generate signals having frequencies that represent difference in inputs, initial weights, and adjusted factors. Frequency detectors are used to compare the oscillator frequencies with a synchronized frequency of all oscillators. The output of the frequency detectors are used to generate the adjusted factors, and in turn generate trained weights.

Abstract: An embodiment includes an apparatus comprising: a first layer and a second layer; a first gate including first gate portions and a second gate including second gate portions; wherein the first layer: (a) is monolithic, (b) is between the first gate portions and is also between the second gate portions, and (c) includes a semiconductor material; wherein the second layer: (a) is between the first layer and at least one of the first gate portions and is also between the first layer and at least one of the second gate portions, and (b) includes oxygen and at least one of hafnium, silicon, yttrium, zirconium, barium, titanium, lead, or combinations thereof; wherein (a) a first plane intersects the first gate portions and the first and second layers, and (b) a second plane intersects the second gate portions and the first and second layers. Other embodiments are described herein.

Abstract: An embodiment includes a system comprising: first, second, third, fourth, fifth, and sixth layers, (a) the second, third, fourth, and fifth layers being between the first and sixth layers, and (b) the fourth layer being between the third and fifth layers; a formation between the first and second layers, the formation including: (a) a material that is non-amorphous; and (b) first and second sidewalls; a capacitor between the second and sixth layers, the capacitor including: (a) the third, fourth, and fifth layers, and (b) an electrode that includes the third layer and an additional electrode that includes the fifth layer; and a switching device between the first and sixth layers; wherein: (a) the first layer includes a metal and the sixth layer includes the metal, and (b) the fourth layer includes a Perovskite material. Other embodiments are addressed herein.

Abstract: Techniques are provided for implementing capsule neural networks (NNs) using vector spin neurons. A vector spin neuron according to an embodiment includes a first magnet, polarized in a first direction, to receive a first input current. The first input current is based on an NN input value and weighting factor. The vector spin neuron also includes a second magnet, polarized in a direction orthogonal to the first direction, to receive a second input current. The second input current is based on a second NN input value and weighting factor. The first and second magnets generate spin polarized currents. In some such embodiments, the vector spin neuron further includes a third magnet, which is unpolarized, and a conductor to couple output regions of the first and second magnets to an input region of the third magnet. The third magnet applies a non-linear activation function to the sum of the spin polarized currents.

Abstract: Techniques are provided for implementing a hybrid processing architecture comprising a general-purpose processor (CPU) coupled to an analog in-memory artificial intelligence (AI) processor. A hybrid processor implementing the techniques according to an embodiment includes an AI processor configured to perform analog in-memory computations based on neural network (NN) weighting factors and input data provided by the CPU. The AI processor includes one or more NN layers. The NN layers include digital access circuits to receive data and weighting factors and to provide computational results. The NN layers also include memory circuits to store data and weights, and further include bit line processors and cross bit line processors to perform analog dot product computations between columns of the data memory circuits and the weight factor memory circuits. Some of the NN layers are configured as convolutional NN layers and others are configured as fully connected NN layers, according to some embodiments.

Abstract: Techniques are provided for implementing a hybrid processing architecture comprising a general-purpose processor (CPU) and a neural processing unit (NPU), coupled to an analog in-memory artificial intelligence (AI) processor. According to an embodiment, the hybrid processor implements an AI instruction set including instructions to perform analog in-memory computations. The AI processor comprises one or more layers, the NN layers including memory circuitry and analog processing circuitry. The memory circuitry is configured to store the weighting factors and the input data. The analog processing circuitry is configured to perform analog calculations on the stored weighting factors and the stored input data in accordance with the execution, by the NPU, of instruction from the AI instruction set. The AI instruction set includes instructions to perform dot products, multiplication, differencing, normalization, pooling, thresholding, transposition, and backpropagation training.

Abstract: A memory device comprises an interconnect comprises a spin orbit coupling (SOC) material. A free magnetic layer is on the interconnect, a barrier material is over the free magnetic layer and a fixed magnetic layer is over the barrier material, wherein the free magnetic layer comprises an antiferromagnet. In another embodiment, memory device comprises a spin orbit coupling (SOC) interconnect and an antiferromagnet (AFM) free magnetic layer is on the interconnect. A ferromagnetic magnetic tunnel junction (MTJ) device is on the AFM free magnetic layer, wherein the ferromagnetic MTJ comprises a free magnet layer, a fixed magnet layer, and a barrier material between the free magnet layer and the fixed magnet layer.

Abstract: A memory device comprises a trench within an insulating layer. A bottom electrode material is along sidewalls and a bottom of the trench, the bottom electrode material conformal to a top surface of the insulating layer. A ferroelectric material is conformal to the bottom electrode. A top electrode material is conformal to the ferroelectric material, wherein the bottom electrode material, the ferroelectric material and the top electrode material all extend above and across the top surface of the insulating layer.

Abstract: Embodiments disclosed herein include transistor devices with complex oxide interfaces and methods of forming such devices. In an embodiment, the transistor device may comprise a substrate, and a fin extending up from the substrate. In an embodiment, a first oxide is formed over sidewall surfaces of the fin, and a second oxide is formed over the first oxide. In an embodiment, the first oxide and the second oxide are perovskite oxides with the general formula of ABO3.

Abstract: An embodiment includes an apparatus comprising: a first layer and a second layer; a first gate including first gate portions and a second gate including second gate portions; wherein the first layer: (a) is monolithic, (b) is between the first gate portions and is also between the second gate portions, and (c) includes a semiconductor material; wherein the second layer: (a) is between the first layer and at least one of the first gate portions and is also between the first layer and at least one of the second gate portions, and (b) includes oxygen and at least one of hafnium, silicon, yttrium, zirconium, barium, titanium, lead, or combinations thereof; wherein (a) a first plane intersects the first gate portions and the first and second layers, and (b) a second plane intersects the second gate portions and the first and second layers. Other embodiments are described herein.

Abstract: An embodiment includes a system comprising: first, second, third, fourth, fifth, and sixth layers, (a) the second, third, fourth, and fifth layers being between the first and sixth layers, and (b) the fourth layer being between the third and fifth layers; a formation between the first and second layers, the formation including: (a) a material that is non-amorphous; and (b) first and second sidewalls; a capacitor between the second and sixth layers, the capacitor including: (a) the third, fourth, and fifth layers, and (b) an electrode that includes the third layer and an additional electrode that includes the fifth layer; and a switching device between the first and sixth layers; wherein: (a) the first layer includes a metal and the sixth layer includes the metal, and (b) the fourth layer includes a Perovskite material. Other embodiments are addressed herein.

Abstract: A memory apparatus is provided which comprises: a stack comprising a magnetic insulating material and a transition metal dichalcogenide (TMD), wherein the magnetic insulating material has a first magnetization. The stack behaves as a free magnet. The apparatus includes a fixed magnet with a second magnetization. An interconnect is further provided which comprises a spin orbit material, wherein the interconnect is adjacent to the stack.

Abstract: Techniques are provided for efficient matrix multiplication using in-memory analog parallel processing, with applications for neural networks and artificial intelligence processors. A methodology implementing the techniques according to an embodiment includes storing two matrices in-memory. The first matrix is stored in transposed form such that the transposed first matrix has the same number of rows as the second matrix. The method further includes reading columns of the matrices from the memory in parallel, using disclosed bit line functional read operations and cross bit line functional read operations, which are employed to generate analog dot products between the columns. Each of the dot products corresponds to an element of the matrix multiplication product of the two matrices. In some embodiments, one of the matrices may be used to store neural network weighting factors, and the other matrix may be used to store input data to be processed by the neural network.

Abstract: Techniques are provided for implementing a recurrent neuron (RN) using magneto-electric spin orbit (MESO) logic. An RN implementing the techniques according to an embodiment includes a first MESO device to apply a threshold function to an input signal provided at a magnetization port of the MESO device, and scale the result by a first weighting factor supplied at an input port of the MESO device to generate an RN output signal. The RN further includes a second MESO device to receive the RN output signal at a magnetization port of the second MESO device and generate a scaled previous RN state value. The scaled previous state value is a scaled and time delayed version of the RN output signal based on a second weighting factor. The RN input signal is a summation of the scaled previous state value of the RN with weighted synaptic input signals provided to the RN.

Abstract: An apparatus is provided which comprises: a magnetic junction having a magnet with perpendicular magnetic anisotropy (PMA) relative to an x-y plane of a device. In some embodiments, the apparatus comprises an interconnect partially adjacent to the structure of the magnetic junction, wherein the interconnect comprises a spin orbit material, wherein the interconnect has a pocket comprising non-spin orbit material, wherein the pocket is adjacent to the magnet of the magnetic junction. In some embodiments, the non-spin orbit material comprises metal which includes one or more of: Cu, Al, Ag, or Au.

Abstract: Described is a method comprising: forming a magnet on a substrate or a template, the magnet having an interface; and forming a first layer of non-magnet conductive material on the interface of the magnet such that the magnet and the layer of non-magnet conductive material are formed in-situ. Described is an apparatus comprising: a magnet formed on a substrate or a template, the magnet being formed under crystallographic, electromagnetic, or thermodynamic conditions, the magnet having an interface; and a first layer of non-magnet conductive material formed on the interface of the magnet such that the magnet and the layer of non-magnet conductive material are formed in-situ.

Abstract: Electrical devices with an integral thermoelectric generator comprising a spin-Seebeck insulator and a spin orbit coupling material, and associated methods of fabrication. A spin-Seebeck thermoelectric material stack may be integrated into macroscale power cabling as well as nanoscale device structures. The resulting structures are to leverage the spin-Seebeck effect (SSE), in which magnons may transport heat from a source (an active device or passive interconnect) and through the spin-Seebeck insulator, which develops a resulting spin voltage. The SOC material is to further convert the spin voltage into an electric voltage to complete the thermoelectric generation process. The resulting electric voltage may then be coupled into an electric circuit.

Abstract: Techniques are provided for radio frequency interconnections between oscillators and transmission lines for oscillatory neural networks (ONNs). An ONN gate implementing the techniques according to an embodiment includes a transmission line, a first oscillator circuit tuned to a first frequency based on a first tuning voltage associated with a first synapse weight, and a first capacitive coupler to couple the first oscillator circuit to the transmission line to generate an oscillating signal in the transmission line. The ONN gate further includes a second oscillator circuit tuned to a second frequency based on a second tuning voltage associated with a second synapse weight, and a second capacitive coupler to couple the second oscillator circuit to the transmission line to adjust the oscillating signal in the transmission line such that the amplitude of the adjusted oscillating signal is associated with a degree of match between the first frequency and the second frequency.