Abstract: Methods and apparatus for complex number generation and operation on a chip are disclosed. A disclosed logic device includes a first magnet with a first preferred direction of magnetization to polarize a spin of electrons in the first direction. The example logic device includes a second magnet with a second preferred direction of magnetization that polarizes a spin of electrons in the second direction. The example logic device includes a third magnet providing a free layer without a preferred direction of magnetization that is connected to the first and second magnets, wherein the third magnet encodes a vector based on a flux of electrons spin polarized in the first direction and a flux of electrons spin polarized in the second direction.

Abstract: A memory device comprises a substrate having a front side and a backside, wherein a first conductive line is on the backside and a second conductive line is on the front side. A transistor is on the front side between the second conductive line and the substrate. A magnetic tunnel junction (MTJ) is on the backside between the first conductive line and the substrate, wherein one end of the MTJ is coupled through the substrate to the transistor and an opposite end of the MTJ is connected to the first conductive line, and wherein the transistor is further connected to the second conductive line on the front side.

Abstract: Embodiments herein relate to magnetically doping a spin orbit torque electrode (SOT) in a magnetic random access memory apparatus. In particular, the apparatus may include a free layer of a magnetic tunnel junction (MTJ) coupled to a SOT electrode that is magnetically doped to apply an effective magnetic field on the free layer, where the free layer has a magnetic polarization in a first direction and where current flowing through the magnetically doped SOT electrode is to cause the magnetic polarization of the free layer to change to a second direction that is substantially opposite to the first direction.

Abstract: An apparatus is provided to improve spin injection efficiency from a magnet to a spin orbit coupling material. The apparatus comprises: a first magnet; a second magnet adjacent to the first magnet; a first structure comprising a tunneling barrier; a third magnet adjacent to the first structure; a stack of layers, a portion of which is adjacent to the third magnet, wherein the stack of layers comprises spin-orbit material; and a second structure comprising magnetoelectric material, wherein the second structure is adjacent to the first magnet.

Abstract: An apparatus is provided which comprises: a stack comprising a magnetic insulating material (MI such as EuS, EuO, YIG, TmIG, or GaMnAs) and a transition metal dichalcogenide (TMD such as MoS2, MoSe2, WS2, WSe2, PtS2, PtSe2, WTe2, MoTe2, or graphene), wherein the magnetic insulating material has a first magnetization; a magnet with a second magnetization, wherein the magnet is adjacent to the TMD of the stack; and an interconnect comprising a spin orbit material, wherein the interconnect is adjacent to the magnet.

Abstract: An apparatus is provided which comprises: a stack comprising a magnetoelectric (ME such as BiFeO3, (LaBi)FeO3, LuFeO3, PMN-PT, PZT, AlN, SmBiFeO3, Cr2O3, etc.) material and a transition metal dichalcogenide (TMD such as MoS2, MoSe2, WS2, WSe2, PtS2, PtSe2, WTe2, MoTe2, graphene, etc.); a magnet adjacent to a first portion of the TMD of the stack; a first interconnect adjacent to the magnet; a second interconnect adjacent to the ME material of the stack; and a third interconnect adjacent to a second portion of the TMD of the stack.

Abstract: An apparatus is provided which comprises: a first stack comprising a magnetic insulating material (MI such as., EuS, EuO, YIG, TmIG, or GaMnAs) and a transition metal dichalcogenide (TMD such as MoS2, MoSe2, WS2, WSe2, PtS2, PtSe2, WTe2, MoTe2, or graphene; a second stack comprising an MI material and a TMD, wherein the first and second stacks are separated by an insulating material (e.g., oxide); a magnet (e.g., a ferromagnet or a paramagnet) adjacent to the TMDs of the first and second stacks, and also adjacent to the insulating material; and a magnetoelectric material (e.g., (LaBi)FeO3, LuFeO3, PMN-PT, PZT, AlN, or (SmBi)FeO3) adjacent to the magnet.

Abstract: A low power, energy efficient, nonvolatile, high-speed memory apparatus is provided that can function at extremely low temperatures (e.g., less than 30 degree Kelvin). The apparatus includes: a first structure comprising a magnet having free or unpinned magnetization; a second structure comprising Type-II multiferroic material, wherein the second structure is adjacent to the first structure; and an interconnect comprising spin orbit material, wherein the interconnect is adjacent to the first structure.

Abstract: An apparatus is provided which comprises: a magnetic junction having a magnet with a first magnetization (e.g., perpendicular magnetization); a first structure adjacent to the magnetic junction, wherein the first structure comprises metal (e.g., Hf, Ta, W, Ir, Pt, Bi, Cu, Mo, Gf, Ge, Ga, or Au); an interconnect adjacent to the first structure; and a second structure adjacent to the interconnect such that the first structure and the second structure are on opposite surfaces of the interconnect, wherein the second structure comprises a magnet with a second magnetization (e.g., in-plane magnetization) substantially different from the first magnetization.

Abstract: An apparatus is provided which comprises: a magnetic junction having a magnet with a magnetization (e.g., a perpendicular magnetization relative to an x-y plane of the apparatus); and an interconnect adjacent to the magnetic junction, wherein the interconnect comprises a chiral antiferromagnetic (AFM) material (e.g., Mn3X, where ‘X’ includes one of: Ge, Sn, Ga, Ir, Rh, or Pt; class-1 kagomi antiferromagnetic material, class-2 hyper kagomi antiferromagnetic material, or metallo-organics).

Abstract: Described is an apparatus which comprises: a first layer formed of a material that exhibits spin orbit torque effect; a second layer formed of material that exhibits spin orbit torque effect; and a magnetic tunneling junction (MTJ) including first and second free magnetic layers, wherein the first free magnetic layer is coupled to the first layer and wherein the second free magnetic layer is coupled to the second layer.

Abstract: Methods and apparatus for complex number generation and operation on a chip are disclosed. A disclosed logic device includes a first magnet with a first preferred direction of magnetization to polarize a spin of electrons in the first direction. The example logic device includes a second magnet with a second preferred direction of magnetization that polarizes a spin of electrons in the second direction. The example logic device includes a third magnet providing a free layer without a preferred direction of magnetization that is connected to the first and second magnets, wherein the third magnet encodes a vector based on a flux of electrons spin polarized in the first direction and a flux of electrons spin polarized in the second direction.

Abstract: Described is an apparatus which comprises: a first layer formed of a material that exhibits spin orbit torque effect; a second layer formed of material that exhibits spin orbit torque effect; and a magnetic tunneling junction (MTJ) including first and second free magnetic layers, wherein the first free magnetic layer is coupled to the first layer and wherein the second free magnetic layer is coupled to the second layer.

Abstract: Described is an interconnect which comprises: a first end having a ferromagnetic layer coupled to a first magnetoelectric material layer; and a second end having a second magnetoelectric material layer coupled to the ferromagnetic layer, wherein the ferromagnetic layer extends from the first end to the second end. Described is a majority gate device which comprises: a ferromagnetic layer; and first, second, third, and fourth magnetoelectric material layers coupled to the ferromagnetic layer. Described is an apparatus which comprises: a first end having a ferromagnetic layer coupled to a first magnetoelectric material layer; and a second end having a tunnel junction device coupled to the ferromagnetic layer. Described is an apparatus which comprises: a first terminal coupled to a tunneling junction device; a second terminal coupled to a layer coupling the tunneling junction device and a magnetoelectric device; and a third terminal coupled to the magnetoelectric device.

Abstract: The present disclosure relates to the fabrication of spin transfer torque memory devices and spin logic devices, wherein a strain engineered interface is formed within at least one magnet within these devices. In one embodiment, the spin transfer torque memory devices may include a free magnetic layer stack comprising a crystalline magnetic layer abutting a crystalline stressor layer. In another embodiment, the spin logic devices may include an input magnet, an output magnet; wherein at least one of the input magnet and the output magnet comprises a crystalline magnetic layer abutting crystalline stressor layer and/or the crystalline magnetic layer abutting a crystalline spin-coherent channel extending between the input magnet and the output magnet.

Abstract: Described is a method comprising: forming a magnet on a substrate or a template, the magnet having an interface; and forming a first layer of non-magnet conductive material on the interface of the magnet such that the magnet and the layer of non-magnet conductive material are formed in-situ. Described is an apparatus comprising: a magnet formed on a substrate or a template, the magnet being formed under crystallographic, electromagnetic, or thermodynamic conditions, the magnet having an interface; and a first layer of non-magnet conductive material formed on the interface of the magnet such that the magnet and the layer of non-magnet conductive material are formed in-situ.

Abstract: Tunneling field effect transistors (TFETs) including a variable bandgap channel are described. In some embodiments, one or more bandgap characteristics of the variable bandgap channel may be dynamically altered by at least one of the application or withdrawal of a force, such as a voltage or electric field. In some embodiments the variable bandgap channel may be configured to modulate from an ON to an OFF state and vice versa in response to the application and/or withdrawal of a force. The variable bandgap channel may exhibit a bandgap that is smaller in the ON state than in the OFF state. As a result, the TFETs may exhibit one or more of relatively high on current, relatively low off current, and sub-threshold swing below 60 mV/decade.

Abstract: An apparatus is described having a select line and an interconnect with Spin Hall Effect (SHE) material. The interconnect is coupled to a write bit line. A transistor is coupled to the select line and the interconnect. The transistor is controllable by a word line. The apparatus also includes an MTJ device having a free magnetic layer coupled to the interconnect.

Abstract: Described is an apparatus for a voltage controlled nano-magnetic random number generator. The apparatus comprises: a free ferromagnetic layer; a fixed ferromagnetic layer positioned in a non-collinear direction relative to the free ferromagnet layer; and a first terminal coupled to the free ferromagnetic layer, the first terminal to provide a bias voltage to the free ferromagnetic layer. Described is also an integrated circuit comprising: a random number generator including a magnetic tunnel junction (MTJ) device with non-collinearly positioned free and fixed ferromagnetic layers; and a circuit to provide an adjustable bias voltage to the free ferromagnetic layer, the circuit to control variance of current generated by the random number generator.

Abstract: An embodiment of the invention includes a memory cell having a magnet layer coupled to a metal layer and read line. The metal layer is also coupled to write and sense lines. During a write operation charge current is supplied to the metal layer via the write line and induces spin current and a magnetic state within the magnet layer based on the spin Hall effect. During a read operation read current is supplied, via the read line, to the magnet layer and then the metal layer and induces another spin current, within the metal layer, that generates an electric field and voltage, based on inverse spin Hall effect, at a sense node coupled to the sense line. The voltage polarity is based on the aforementioned magnetic state. The memory operates with a low supply voltage to drive charge, read, and spin currents. Other embodiments are described herein.