Abstract: A tool that enables a user to perform instruction operand tracing during debug is presented. While executing microcode on a simulator, a history of register and memory values is saved. A graphic user interface uses these values to present a view of the microcode in a thread history. The user can use the thread history to select any given cycle time of the simulation, and switch over to a thread window (or code list view). The instruction that executed at the cycle of interest is marked in the code list view, and right-clicking on the code line, the user is given options, including an option to jump backward in time to the code line where a source variable was set and/or the option to jump forward in time to a code line that used a result variable.

Abstract: In general, in one aspect, a method is provided for of tracking a network statistic stored within a collection of bits. The method includes storing the collection of bits storing the network statistic as at least a first portion and a second portion. The first portion includes a set of least-significant bits and the second portion includes a set of more significant bits. The method also includes incrementing the first portion based on a packet and determining if the incrementing of the first portion caused a designated bit of the first portion to be set. If it is determined that the incrementing of the first portion caused the designated bit to be set, the method increments the value stored by the second portion and resets the designated bit within the first portion.

Abstract: The disclosure includes description of techniques for processing a network packet received at a network device. An example of the technique includes, in a first path, performing packet processing phases upon the network packet and storing state data for the phase phases. A second path can access the state data stored by the first path and determine a phase to perform next.

Abstract: A mechanism to process units of data associated with a dependent data stream using different threads of execution and a common data structure in memory. Accessing the common data structure in memory for the processing uses a single read operation and a single write operation. The folding of multiple read-modify-write memory operations in such a manner for multiple multi-threaded stages of processing includes controlling a first stage, which operates on the same data unit as a second stage to pass context state information to the second stage for coherency.

Abstract: A method and apparatus for transmitting network traffic includes selecting a major node in a major ring, where the major node corresponds to a first transmission opportunity encoded in the major ring. The major node specifies a minor node in a minor ring representing a virtual port. The method and apparatus also includes transmitting network traffic to a virtual connection that uses the virtual port. Alternatively, transmitting network traffic involves processing a schedule that includes a sequence of transmission opportunities encoded in a schedule ring and satisfying a minimum data rate for a scheduled virtual connection by processing a corresponding first minimum number of transmission opportunities from the schedule, each such transmission opportunity allocated by a schedule node to the scheduled virtual connection, where the schedule node is included in the schedule ring.

Abstract: A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.

Abstract: The disclosure includes description of a method of processing packets using threads. The method includes processing a packet by a single thread in a first packet processing pipeline stage and processing the packet by multiple threads in a second packet processing pipeline stage.

Abstract: A method of managing queue entries includes storing addresses in a first queue entry as a linked list, each of the stored addresses including a cell count, retrieving a first address from the first queue entry, and modifying the linked list of addresses of the first queue entry based on the cell count of the first address retrieved.

Abstract: A network packet may be forwarded by reading a table containing a plurality of flags to determine which of the plurality of flags is set or cleared and performing an operation on the packet to decapsulate or encapsulate the packet in accordance with values of the flags.

Abstract: The disclosure includes description of a technique for processing a network packet at a device. The technique can include accessing an entry for a packet in one of a plurality of source queues and, based on the accessed entry, determining whether to queue an entry for the packet in at least one of a plurality of destination queues.

Abstract: A method of searching a database for a prefix representing a destination address including loading two trees of tables, each tree of tables having a large table at a root branching to small tables and traversing the two tables of trees in parallel to find a match of an entry to the prefix. An entry includes a router pointer representing the destination address and a pointer to a next small table. The small tables include prefix match fields for indexed table entries, a population count of pointers and hidden prefix entries that hold shorter prefix route entry pointers.

Abstract: Method and apparatus for performing centralized cyclic redundancy checks (CRC). For one embodiment a current thread of execution compares a connection index with that of a previous thread of execution. If they share the same connection index, a CRC calculation may be performed without providing a CRC residue to a centralized CRC unit since the most recently produced CRC residue by would be associated with a preceding sequential cell of the same packet. For an alternative embodiment a current thread of execution requests a CRC calculation and provides a connection index to the centralized CRC unit, which is used to access a content addressable memory (CAM). A hit in the CAM indicates that the CRC unit may use the CRC residue associated with the connection index in the CAM since it would have resulted from a preceding sequential cell.

Abstract: The disclosure includes description of a technique for use in looking-up data based on content of a packet received over a network. The technique includes receiving a lookup value based on the received packet, searching a first memory using at least a portion of the lookup value, and if the searching the first memory fails, searching a second memory, having a lower latency than the first memory, using at least a portion of the lookup value.

Abstract: A switch for transmitting data from a first device to a second device includes a port in communication with the second device, queues which store slices of data received from the first device, and circuitry for selectively outputting a slice of the data from at least one of the queues to the port for transmission to the second device.

Abstract: A method of debugging code that executes in a multithreaded processor having a microengines includes receiving a program instruction and an identification representing a selected one of the microengines from a remote user interface connected to the processor pausing program execution in the threads executing in the selected microengine, inserting a breakpoint after a program instruction in the selected microengine that matches the program instruction received from the remote user interface, resuming program execution in the selected microengine, executing a breakpoint routine if program execution in the selected microengine encounters the breakpoint and resuming program execution in the microengine.

Abstract: Applications software can be rapidly tested and developed for a multi-processor chip even though the hardware of new processors of the multi-processor chip is not yet available. This can be accomplished by executing software simulations of the new processor designs and corresponding applications software either on a previously designed processor that is hardware on the multi-processor chip or on a workstation development platform. The execution of the previously designed processor is typically much faster than the execution on a simulator running on a personal workstation development platform, and therefore the execution time is quicker. Furthermore, the processor simulation and application software can be configured to take advantage of the platform most appropriate for execution and avoid simulation of portions of the new processors that are not necessary for testing the applications software.

Abstract: A method of transmitting data packets includes using one or more receive processors to receive a plurality of data packets from a network and processing the plurality of data packets using a management processor. The method also includes using one or more transmit processors to transmit packets to the network.

Abstract: A method of processing network data in a network processor includes using three or more threads to process a beginning portion, a middle portion, and an end portion of data packet. The first thread processes the beginning portion; one or more middle threads process the middle portion, and a last thread processes the end portion. First information is indirectly passed from the first thread to the last thread via a first buffer with the middle threads progressively updating the first information. Second information is directly passed from the first thread to the last thread via a second buffer.

Abstract: A method of forwarding data out of a processor includes receiving data by the processor, then using two schedulers to assign processing threads to transmit data out of the processor. Each of the schedulers supports forwarding data out of ports that are mutually exclusive from those of the other scheduler. The processing threads can operate at least partially simultaneously.

Abstract: A method of debugging software that executes in a multithreaded processor having a plurality of microengines includes pausing program execution in threads of execution within a target microengine, inserting a segment of executable code into an unused section of the target microengine's microstore, executing the segment of executable code in the target microengine and resuming program execution in the target microengine