Abstract: An apparatus and method for memory allocation with digital processing systems comprises a first memory bank, a hardware register, and a processing circuit configured to write the contents of the hardware register to a memory address in the first memory bank, and to write the memory address to the hardware register. In an embodiment, a pointer list containing memory pointer values may be maintained in the first memory bank. The first memory bank may contain associated data buffers, and a second memory bank may contain corresponding data buffers such that an associated data buffer and a corresponding data buffer may be located from a single memory pointer value.

Abstract: A system and method for controlling transmission of cells is described. The cells are associated with virtual circuits that either require shaping according to constant bit rate (CBR) or real-time variable bit rate (rt-VBR), or no shaping with transmit selection based on priority (for services other than CBR and rt-VBR). The system transmits the shaped and unshaped traffic using one or more circular control structures. The control structures have time slots at the granularity of the maximum system transmit rate.

Abstract: A network processor that has multiple processing elements, each processing element supporting multiple simultaneous program threads with access to shared resources in an interface. Packet data is received from high-speed ports in segments and each segment is assigned to one of the program threads. Each packet may be assigned to a single program thread, two program threads, or a different program thread for segment of data in a packet. For the two program threads, one program thread can be used for header segment processing and the other program thread can be used for handling payload segment(s). Dedicated inputs for ready status and sequence numbers can provide assistance for receiving the packet data over a high speed port. The dedicated inputs are used to monitor ready flags from the high speed ports on a cycle-by-cycle basis. The sequence numbers are used by the assigned threads to maintain ordering of segments within a packet, as well as to order the writes of the complete packets to transmit queues.

Abstract: A graphical user interface (GUI) includes state indicators which show states of execution of threads running in microengines of a processor. The state indicators show the states of execution as functions of clocking in the processor. The GUI also includes a window showing computer code corresponding to one of the threads.

Abstract: A method of managing queue entries includes storing addresses in a first queue entry as a linked list, each of the stored addresses including a cell count, retrieving a first address from the first queue entry, and modifying the linked list of addresses of the first queue entry based on the cell count of the first address retrieved.

Abstract: A method of forwarding a network packet is described. The method includes reading a table containing a plurality of flags to determine which of the plurality of flags is set or cleared and performing an operation on the packet to decapsulate or encapsulate the packet in accordance with values of the flags.

Abstract: An apparatus and method for memory allocation with digital processing systems comprises a first memory bank, a hardware register, and a processing circuit configured to write the contents of the hardware register to a memory address in the first memory bank, and to write the memory address to the hardware register. In an embodiment, a pointer list containing memory pointer values may be maintained in the first memory bank. The first memory bank may contain associated data buffers, and a second memory bank may contain corresponding data buffers such that an associated data buffer and a corresponding data buffer may be located from a single memory pointer value.

Abstract: A method of transmitting data packets includes using one or more receive processors to receive a plurality of data packets from a network and processing the plurality of data packets using a management processor. The method also includes using one or more transmit processors to transmit packets to the network.

Abstract: A method and mechanism for executing an application by a processor in a multi-processor configuration of processors, each having an associated instruction memory is presented. The application receives object code that includes an image for at least one other processor in the multi-processor configuration of processors. The application binds an import variable in the image to a parameter value and stores the image for the at least one other processor into the associated instruction memory.

Abstract: A switch for transmitting data from a first device to a second device includes a port in communication with the second device, queues which store slices of data received from the first device, and circuitry for selectively outputting a slice of the data from at least one of the queues to the port for transmission to the second device.

Abstract: Applications software can be rapidly tested and developed for a multi-processor chip even though the hardware of new processors of the multi-processor chip is not yet available. This can be accomplished by executing software simulations of the new processor designs and corresponding applications software either on a previously designed processor that is hardware on the multi-processor chip or on a workstation development platform. The execution of the previously designed processor is typically much faster than the execution on a simulator running on a personal workstation development platform, and therefore the execution time is quicker. Furthermore, the processor simulation and application software can be configured to take advantage of the platform most appropriate for execution and avoid simulation of portions of the new processors that are not necessary for testing the applications software.

Abstract: A method of operating a processor including loading one or more bytes of data within a register associated with microengines with a shifted value of an operand and preserving or clearing the bytes of data that are not loaded. The method further includes providing a bit mask that specifies which of the one or more bytes of data within the register are affected.

Abstract: A data base is created by storing a plurality of data objects in a memory. Each data object has attributes including a key value and a data value. The data objects are partitioned into a plurality of classes, each class having one or more members, each member including the same attributes of the data objects. An access method is defined for at least one member of a specific class to access the data objects of the specific class by key values. For another member of the specific class, an access method to access the data objects of a related class is defined. A specific data value of a specific data object is compared with the key values of the data objects of the related class, and if the specific data value is equal to the key value of a related data object a memory address of the related data object is associated with the specific data value.

Abstract: In a distributed interactive multimedia service system, a client application of a set-top box located at a customer premises generates an attach request. A session manager, in response to receiving the attach request via a network, generates an allocation request and a create request. A resource manager, in response to the allocation request, allocates resources of a plurality of multimedia servers. The resources can include processor, memory, disk, and network resources. A media stream manager, in response to the create request, creates a multimedia stream. The session manager, in response to the resources being allocated, and the multimedia stream being created, launches a selected one of a plurality of multimedia services in the plurality of multimedia servers. The selected service provides multimedia information to the set-top box via the multimedia stream.

Abstract: An interactive video system employs Motion Picture Expert Group (MPEG) video compression to transfer images from a remote server to a television. The images correspond to dialog frames in a graphical user interface. During an authoring process, the dialog frames are created by first creating a background image and then adding foreground elements, such as buttons. A set of MPEG video frames is created by encoding the resulting images according to the MPEG algorithm. The MPEG video frames are delivered to the television in sequence, where an MPEG decoder uses them to reconstruct the dialog images that are subsequently displayed. The system also contains an object-oriented database that maintains the necessary MPEG file ordering and also carries out menu navigation commands received from the user. The object classes include NODE, BRANCH, and DISPLAY. NODE objects correspond to dialog frames, and BRANCH objects correspond to user-selectable features such as buttons.

Abstract: In the synthesis procedure for circuit design, a convenient notation is used for the insertion of new instances in the consequence portion of a rule having a antecedent form and a consequence portion. The notation is of the form(outputs . . . )=(operator inputs . . . ).The outputs and inputs may be signal names or data base pin access forms. Double quoted strings of characters can represent specific signals in the global design model. Double quoted strings of characters including the % character can be used for local connectivity among logic elements representing multiple equations inserted by the rule. The equations are converted to model instance structures and are inserted into the data base. Creation of database pointers are generated automatically and not by the rule writer, greatly simplifying the rule syntax.

Abstract: In a system for interactively viewing videos, a selected video is transmitted as a plurality of frames of digitized video data for playback on a viewing device. The system receives the transmitted video data and includes a memory buffer for storing a segment of a selected one of the videos. The segment includes a predetermined number of frames representing a predetermined time interval of the selected video. In addition, the memory buffer including a write pointer and a read pointer. Software controlled servers are provided for witting and reading video data of the selected video to and from the memory buffer, independently, at locations indicated by the write and read pointers to transfer the selected video to the viewing device. By using a remote controller the viewer can position the read and write pointers to view any portion of the selected video interactively.

Abstract: An interactive video system employs Motion Picture Expert Group (MPEG) video compression to transfer images from a remote server to a television. The images correspond to dialog frames in a graphical user interface. During an authoring process, the dialog frames are created by first creating a background image and then adding foreground elements, such as buttons. A set of MPEG video frames is created by encoding the resulting images according to the MPEG algorithm. The MPEG video frames are delivered to the television in sequence, where an MPEG decoder uses them to reconstruct the dialog images that are subsequently displayed. The system also contains an object-oriented database that maintains the necessary MPEG file ordering and also carries out menu navigation commands received from the user. The object classes include NODE, BRANCH, and DISPLAY. NODE objects correspond to dialog frames, and BRANCH objects correspond to user-selectable features such as buttons.

Abstract: In a system for distributing videos, a plurality of videos are stored on a mass storage device. Each video includes a plurality of frames of digitized video data for play-back on a viewing device. The system includes a memory buffer for storing a segment of a selected one of the videos. The segment includes a predetermined number of frames representing a predetermined time interval of the selected video. In addition, the memory buffer including a write pointer and a read pointer. Software controlled servers are provided for witting and reading video data of the selected video to and from the memory buffer, independently, at locations indicated by the write and read pointers to transfer the selected video to the viewing device.

Abstract: In a circuit design synthesis procedure in which the pointers are added to the data base to permit a path through the circuit to be followed, a qualified object is defined to be a data object that permits access expressed by a sequence (or chain) of access forms strung together. A mechanism is defined that permits access of any object in a logic design database relative to any other object in the data base. Access forms are strung together in a given format. This structure provides an easily understandable access form and it is defined in the rule grammar. This access form can be parsed in the synthesis procedure into a nest of (LISP) program functions, which, when evaluated, will return an object in the data base. This access chain is used in the antecedent and consequence portions of the rule structure for the purpose of modifying the target objects. This access structure permits the synthesis rules to make decisions on such parameters as timing, cell size, power, wire loading, model names, etc.