Abstract: In a procedure for synthesizing circuit designs, a SYNTHESIZE command in a consequence portion of a rule can be used to control the creation of bit-level instances from a description of a more abstract instance whose interface consists of multi-bit signals. The `synthesize` command has a form that identifies multibit signal/part objects in the data base relative to the current multi-bit instance, which are then synthesized over the range of most-significant to least significant bit. A collection of rules, called macrorules are enclosed within a `synthesize` command. An iteration controlled by "current bit", ranging from least significant to most significant bit, ensues. At each step of the iteration, all macrorules are tested and applied if they are `true`. The macrorules can query whether the current bit is a function of the least or most significant bits. The macrorules can also establish connectivity to any signal bit relative to the current, the least significant or the most significant bit.

Abstract: A procedure is described for the synthesis and transformation of a logic circuit design, provided by the designers, into a database capable of being used to fabricate the actual circuit. The procedure involves the use of model instances which represent the use of circuit components. The original model instances can be associated with groups of rules that determine resulting configurations of generally different model instances or groups of model instances. The rules are tested and, in the presence of a `true` result, a new model instance (or model instances) can replace one or more original model instances in the data base. The rules associated with a model type (or definition) are rules derived by a design model engineer and can include coupled model instances. The rules can be associated with model definitions, as well as model instances.

Abstract: In a procedure for the synthesis of logic circuits in which the components of the logic circuits are replaced by model instances related to data files stored in the procedure data base, a rule structure is described that permits the synthesis of the logic circuit by testing the model instances through a process included in a first or antecedent portion of the rule, and in the event that the conditions of the rule are fulfilled, then the consequence portion of the rule is executed. The consequence portion of the rule can include the replacement of one or more model instances of the logic circuit with one or more different model instances while retaining the functional or logical equivalence between the instances before and after the application of the rule. The rule includes a field that permits automatic prioritization a plurality of rules. The rules are written in a format that is similar to normal grammatical construction and, therefore, easily learned.

Abstract: The invention comprises a method for the synthesis of a logic circuit by a data processing system in which a plurality of circuit components are examined and are changed in accordance with preestablished rules, and in which timing parameters are estimated for selected circuit locations. Forward timing delays are determined by adding the timing delays associated with the intervening circuit components and media paths between an input terminal or latch component output terminals and successive locations on the signal path. Similarly, a derived budget timing delay constant is calculated by designating a budget or design delay at any location in the circuit and by subtracting timing delays associated with the intervening components between that location and the previous location along the signal path in the reverse direction. The derived budget timing delay constant is subtracted from the forward timing delay at each selected location to derive a timing debt for each selected location.

Abstract: A method for simplifying Boolean AND-OR logic in a circuit synthesis system. Rules are associated with model instances representing circuit components and contained in a data base. During testing of an antecedent portion of a rule, a benefit value representing a decrease in pins or an improvement in timing is calculated and compared to the value of a "benefit variable", which represents a minimum acceptable benefit that must be gained from application of a rule. If a sufficient benefit will result from application of the rule, the rule is applied. Some rules simplify the circuit and then recursively call themselves. Some rules indicate other model instances in the data base, search the set of rules for rules applicable to that model instance, and apply the rule discovered during the search.

Abstract: A logic method for automatically adding new parameters to a data base in a logic synthesis system. Initially, parameter definitions are input to the system and stored in a parameter definition table and used to create functions for accessing the parameter values associated with various components (model instances) in the data base. Both singular and plural access functions are generated for accessing single parameter values and lists of parameter values, respectively. A SETF function for modifying the parameter values is also generated from information in the parameter definition. Parameter values can be inherited from one model instance by another model instance. Each model instance in the data base has a dynamic parameter list associated therewith. Each dynamic parameter list contains entries of parameter name/value pairs. During circuit synthesis, the parameter values of various ones of these entries are modified using the SETF function, which was automatically generated previously.

Abstract: A microprogrammed data processing system uses a plurality of control stores to control the data processing system in response to a macroinstruction sequence. Between each control store is a latch element resulting in a given address being applied to each control store at different system clock cycles. The corresponding microinstruction segment from each control store is therefore provided at different clock cycles, making it possible to coordinate the microinstruction segment with the corresponding flow of data through the central processing unit. The use of a plurality of control stores can reduce the number of gate elements needed to delay microinstruction segments.

Abstract: Address circuitry generates groups of tag signals, and each group is associated with a data word in a data processing device. A portion of the tag signals defines an addressable location in a storage device and another portion of the tag signals defines an operational identification of its associated data word. As data words (i.e., instruction words, operands, etc.) are fetched from memory they are decoded, if necessary, or made ready, (for use by the circuitry which executes the operations intended for such instructions, operands, etc.), and are stored in a multi-plane set of buffers. Each of said buffers has a plurality of address locations, corresponding to the address locations defined by said first portions of said tag signals, and each of said planes is selectable by said other portions of said tag signals.