Abstract: In general, in one aspect, the disclosure describes a method of enqueuing and dequeuing queue entries for protocol data units. The method includes assigning a queue from a set of queues to a received protocol data unit, determining a queue from the set of queues to dequeue based on a scheduling policy, and adjusting a count of entries of the queue to dequeue and the queue assigned to the protocol data unit. After the adjusting, the method includes enqueuing an entry for the received protocol data unit in the assigned queue and dequeueing an entry in the queue to dequeue.

Abstract: A device and method for processing a data packet at a device are described. The device receives data packets and determines available memory in one or more of local memories of a plurality of execution threads. The device stores packet information in an available one of the local memories of the execution threads.

Abstract: In general, in one aspect, the disclosure describes a method that includes accessing a semaphore within a first set of semaphores. Individual semaphores within the first set identify whether a thread processing a first packet is blocked from executing sections of instructions associated with the individual semaphores. The method also includes changing the value of at least one semaphore within a second set of semaphores that identify whether a thread processing a second packet is blocked from executing sections of instructions associated with the individual semaphores.

Abstract: An apparatus and method for memory allocation with digital processing systems comprises a first memory bank, a hardware register, and a processing circuit configured to write the contents of the hardware register to a memory address in the first memory bank, and to write the memory address to the hardware register. In an embodiment, a pointer list containing memory pointer values may be maintained in the first memory bank. The first memory bank may contain associated data buffers, and a second memory bank may contain corresponding data buffers such that an associated data buffer and a corresponding data buffer may be located from a single memory pointer value.

Abstract: A method of debugging code that executes in a multithreaded processor having a microengines includes receiving a program instruction and an identification representing a selected one of the microengines from a remote user interface connected to the processor pausing program execution in the threads executing in the selected microengine, inserting a breakpoint after a program instruction in the selected microengine that matches the program instruction received from the remote user interface, resuming program execution in the selected microengine, executing a breakpoint routine if program execution in the selected microengine encounters the breakpoint and resuming program execution in the microengine.

Abstract: A method of debugging software that executes in a multithreaded processor having a plurality of microengines includes pausing program execution in threads of execution within a target microengine, inserting a segment of executable code into an unused section of the target microengine's microstore, executing the segment of executable code in the target microengine and resuming program execution in the target microengine

Abstract: In general, in one aspect, the disclosure describes a technique of determining forwarding information for at least a sub-set of members of a multicast group, and sending, toward a downstream entity, at most a single copy of data to be multicasted to the sub-set of members and the determined forwarding information.

Abstract: An apparatus and method for memory allocation with digital processing systems comprises a first memory bank, a hardware register, and a processing circuit configured to write the contents of the hardware register to a memory address in the first memory bank, and to write the memory address to the hardware register. In an embodiment, a pointer list containing memory pointer values may be maintained in the first memory bank. The first memory bank may contain associated data buffers, and a second memory bank may contain corresponding data buffers such that an associated data buffer and a corresponding data buffer may be located from a single memory pointer value.

Abstract: The disclosure includes description of a method of processing packets using threads. The method includes processing a packet by a single thread in a first packet processing pipeline stage and processing the packet by multiple threads in a second packet processing pipeline stage.

Abstract: A graphical user interface (GUI) includes state indicators which show states of execution of threads running in microengines of a processor. The state indicators show the states of execution as functions of clocking in the processor. The GUI also includes a window showing computer code corresponding to one of the threads.

Abstract: Providing flow control includes receiving at a router an indication of the ability of each one of multiple ports not directly connected to the router to receive data from the router and controlling transmission of data from the router to the multiple ports based at least on the indication.

Abstract: A network processor that has multiple processing elements, each supporting multiple simultaneous program threads with access to shared resources in an interface. Packet data is received from high-speed ports in segments and each segment is assigned to one of the program threads. Each packet may be assigned to a single program thread, two program threads—one for header segment processing and the other for handling payload segment(s)—or a different program thread for segment of data in a packet. Dedicated inputs for ready status and sequence numbers provide assistance needed for receiving the packet data over a high speed port. The dedicated inputs are used to monitor ready flags from the high speed ports on a cycle-by-cycle basis. The sequence numbers are used by the assigned threads to maintain ordering of segments within a packet, as well as to order the writes of the complete packets to transmit queues.

Abstract: A method and apparatus for transmitting network traffic includes selecting a major node in a major ring, where the major node corresponds to a first transmission opportunity encoded in the major ring. The major node specifies a minor node in a minor ring representing a virtual port. The method and apparatus also includes transmitting network traffic to a virtual connection that uses the virtual port. Alternatively, transmitting network traffic involves processing a schedule that includes a sequence of transmission opportunities encoded in a schedule ring and satisfying a minimum data rate for a scheduled virtual connection by processing a corresponding first minimum number of transmission opportunities from the schedule, each such transmission opportunity allocated by a schedule node to the scheduled virtual connection, where the schedule node is included in the schedule ring.

Abstract: The disclosure includes description of a technique for use in looking-up data based on content of a packet received over a network. The technique includes receiving a lookup value based on the received packet, searching a first memory using at least a portion of the lookup value, and if the searching the first memory fails, searching a second memory, having a lower latency than the first memory, using at least a portion of the lookup value.

Abstract: A machine-based method includes scheduling data units into respective time slots of reservation groups by representing the time slots in a base vector. The time slots of each of the reservation groups corresponds to a contiguous block in the base vector. Groups of time slots are represented in a higher-level vector having fewer elements than the base vector.

Abstract: A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.

Abstract: The disclosure includes description of a technique for processing a network packet at a device. The technique can include accessing an entry for a packet in one of a plurality of source queues and, based on the accessed entry, determining whether to queue an entry for the packet in at least one of a plurality of destination queues.

Abstract: The disclosure includes description of techniques for processing a network packet received at a network device. An example of the technique includes, in a first path, performing packet processing phases upon the network packet and storing state data for the phase phases. A second path can access the state data stored by the first path and determine a phase to perform next.

Abstract: A method and mechanism for executing an application by a processor in a multi-processor configuration of processors, each having an associated instruction memory is presented. The application receives object code that includes an image for at least one other processor in the multi-processor configuration of processors. The application binds an import variable in the image to a parameter value and stores the image for the at least one other processor into the associated instruction memory.

Abstract: A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.