Patents by Inventor Edgar R. Cordero
Edgar R. Cordero has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9501432Abstract: A first memory buffer has a first high speed memory channel and a second high speed memory channel. A second memory buffer is connected to the first memory buffer through a first connection. The second memory buffer has a third high speed memory channel and a fourth high speed memory channel. The first connection connects the first high speed memory channel and the third high speed memory channel. A first memory controller is connected to the first memory buffer through the second high speed memory channel. A second memory controller is connected to the second memory buffer through a second connection. The second connection is connected to the second memory buffer through the fourth high speed memory channel. A first memory module set is connected to the first memory buffer and a second memory module set is connected to the second memory buffer.Type: GrantFiled: April 7, 2014Date of Patent: November 22, 2016Assignee: International Business Machines CorporationInventors: Edgar R. Cordero, Girisankar Paulraj, Diyanesh B. Chinnakkonda Vidyapoornachary
-
Patent number: 9471540Abstract: A computer determines a threshold signal voltage of a semiconductor device. The computer determines a first expected signal propagation time for a signal travelling through a first test path of the semiconductor device. The computer transmits a first signal through the first test path. The computer measures a signal voltage and signal propagation time of the first signal. The computer determines that the signal voltage of the first signal does not reach or exceed the threshold signal voltage within the first expected signal propagation time. The computer determines that the first test path contains a defect.Type: GrantFiled: January 3, 2013Date of Patent: October 18, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Edgar R. Cordero, Anand Haridass, Girisankar Paulraj, Diyanesh B. Vidyapoornachary
-
Patent number: 9471239Abstract: According to embodiments of the disclosure, methods, systems and computer program products for memory power management and data consolidation are disclosed. The method may include selecting a first real memory portion and a second real memory portion from a plurality of real memory portions coupled to a memory controller in a computer system by a memory bus. The first real memory portion may be connected to a first buffer and the second real memory portion may be connected to a second buffer. The first and second real memory portions may be selected by the memory controller. The method may include migrating data from the first real memory portion to the second real memory portion on a migration bus through the first and second buffers. The method may also include placing the first real memory portion into a reduced power mode.Type: GrantFiled: April 26, 2016Date of Patent: October 18, 2016Assignee: International Business Machines CorporationInventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Edgar R. Cordero, Anand Haridass, Arun Joseph
-
Patent number: 9442816Abstract: A method, system and computer program product implement memory performance management and enhanced memory reliability of a computer system accounting for system thermal conditions. When a primary memory temperature reaches an initial temperature threshold, reads are suspended to the primary memory and reads are provided to a mirrored memory in a mirrored memory pair, and writes are provided to both the primary memory and the mirrored memory. If the primary memory temperature reaches a second temperature threshold, write operations to the primary memory are also stopped and the primary memory is turned off with DRAM power saving modes such as self timed refresh (STR), and the reads and writes are limited to the mirrored memory in the mirrored memory pair. When the primary memory temperature decreases to below the initial temperature threshold, coherency is recovered by writing a coherent copy from the mirrored memory to the primary memory.Type: GrantFiled: November 30, 2011Date of Patent: September 13, 2016Assignee: International Business Machines CorporationInventors: Edgar R. Cordero, Timothy J. Dell, Joab D. Henderson, Anil B. Lingambudi, Girisankar Paulraj, Diyanesh B. Vidyapoornachary
-
Patent number: 9418722Abstract: A method and apparatus for refreshing a row of a memory device prior to a scheduled refresh. A memory array may include a plurality of memory cells. The memory array may be configured to be refreshed at a first refresh time interval. The memory device may also include an intermediate refresh circuit. The intermediate refresh circuit may be configured to detect a triggering event and request a refresh for a row of the memory array in response to detecting a triggering event.Type: GrantFiled: October 8, 2015Date of Patent: August 16, 2016Assignee: International Business Machines CorporationInventors: Edgar R. Cordero, Joab D. Henderson, Kyu-hyoun Kim, Jeffrey A. Sabrowski, Anuwat Saetow
-
Publication number: 20160223222Abstract: A method, system and computer program product for implementing thermal air flow control management of a computer system. A temperature profile of the server system is identified. One or more dual in-line memory-modules (DIMMs) are used to pivot on an axis to direct air flow to cool identified hot spots based upon the temperature profile of the server system.Type: ApplicationFiled: February 2, 2015Publication date: August 4, 2016Inventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Edgar R. Cordero, Saravanan Sethuraman
-
Publication number: 20160224265Abstract: According to embodiments of the disclosure, methods, systems and computer program products for memory power management and data consolidation are disclosed. The method may include selecting a first real memory portion and a second real memory portion from a plurality of real memory portions coupled to a memory controller in a computer system by a memory bus. The first real memory portion may be connected to a first buffer and the second real memory portion may be connected to a second buffer. The first and second real memory portions may be selected by the memory controller. The method may include migrating data from the first real memory portion to the second real memory portion on a migration bus through the first and second buffers. The method may also include placing the first real memory portion into a reduced power mode.Type: ApplicationFiled: April 26, 2016Publication date: August 4, 2016Inventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Edgar R. Cordero, Anand Haridass, Arun Joseph
-
Publication number: 20160224079Abstract: A method, system and computer program product for implementing thermal air flow control management of a computer system. A temperature profile of the server system is identified. One or more dual in-line memory-modules (DIMMs) are used to pivot on an axis to direct air flow to cool identified hot spots based upon the temperature profile of the server system.Type: ApplicationFiled: April 25, 2015Publication date: August 4, 2016Inventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Edgar R. Cordero, Saravanan Sethuraman
-
Patent number: 9349432Abstract: A method and apparatus for modifying a reference voltage between refreshes in a memory device are disclosed. The memory array may include a plurality of memory cells. The memory device may also include a sense amplifier. The sense amplifier may be configured to read data from the plurality of memory cells using a reference voltage. The memory device may also include a sense amplifier reference voltage modification circuit. The sense amplifier reference voltage modification circuit may be configured to detect a triggering event and modify the reference voltage in response to detecting a triggering event.Type: GrantFiled: April 23, 2015Date of Patent: May 24, 2016Assignee: International Business Machines CorporationInventors: Edgar R. Cordero, Joab D. Henderson, Kyu-hyoun Kim, Jeffrey A. Sabrowski, Anuwat Saetow
-
Patent number: 9348744Abstract: A method, system and computer program product are provided for implementing enhanced reliability of memory subsystems utilizing a dual port Dynamic Random Access Memory (DRAM) configuration. The DRAM configuration includes a first buffer and a second buffer, each buffer including a validity counter. The validity counter for a receiving buffer is incremented as each respective data row from a transferring buffer is validated through Error Correction Code (ECC), Reliability, Availability, and Serviceability (RAS) logic and transferred to the receiving buffer, while the validity counter for the transferring buffer is decremented. Data are read from or written to either the first buffer or the second buffer based upon a respective count value of the validity counters.Type: GrantFiled: June 23, 2014Date of Patent: May 24, 2016Assignee: International Business Machines CorporationInventors: Edgar R. Cordero, Carlos A. Fernandez, Joab D. Henderson, Jeffrey A. Sabrowski, Anuwat Saetow, Saravanan Sethuraman
-
Patent number: 9305618Abstract: A method, system and memory controller are provided for implementing simultaneous read and write operations in a memory subsystem utilizing a dual port Dynamic Random Access Memory (DRAM) configuration. A DRAM includes a first partition and a second partition. A memory controller determines if memory requirements are above or below a usage threshold. If the memory requirements are below the usage threshold, the memory is partitioned into a read buffer and a write buffer, with writes going to the write buffer and reads coming from the read buffer, data being transferred from the write buffer to the read buffer through an Error Correction Code (ECC) engine. If the memory requirements are above the usage threshold, the entire memory is used for reads and writes.Type: GrantFiled: January 30, 2014Date of Patent: April 5, 2016Assignee: International Business Machines CorporationInventors: Edgar R. Cordero, Carlos A. Fernandez, Joab D. Henderson, Jeffrey A. Sabrowski, Anuwat Saetow, Saravanan Sethuraman
-
Patent number: 9305619Abstract: A method, system and memory controller are provided for implementing simultaneous read and write operations in a memory subsystem utilizing a dual port Dynamic Random Access Memory (DRAM) configuration. A DRAM includes a first partition and a second partition. A memory controller determines if memory requirements are above or below a usage threshold. If the memory requirements are below the usage threshold, the memory is partitioned into a read buffer and a write buffer, with writes going to the write buffer and reads coming from the read buffer, data being transferred from the write buffer to the read buffer through an Error Correction Code (ECC) engine. If the memory requirements are above the usage threshold, the entire memory is used for reads and writes.Type: GrantFiled: June 20, 2014Date of Patent: April 5, 2016Assignee: International Business Machines CorporationInventors: Edgar R. Cordero, Carlos A. Fernandez, Joab D. Henderson, Jeffrey A. Sabrowski, Anuwat Saetow, Saravanan Sethuraman
-
Patent number: 9300298Abstract: A method of configuring a plurality of configurable integrated circuit dies including receiving a configuration data stream at a die stack. The configuration data stream includes configuration memory data for logic devices located on dies in the die stack. At least two of the dies are located on different substrates. The method also includes, performing for each of the dies in the die stack: receiving the configuration memory data for the die, storing the configuration memory data for the die in a configuration memory on the die, determining whether the configuration data stream includes configuration memory data for an additional die in the die stack, and transmitting the configuration data stream to the additional die in the die stack in response to the configuration data stream including configuration memory data for the additional die in the die stack.Type: GrantFiled: June 11, 2013Date of Patent: March 29, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Edgar R. Cordero, Robert B. Tremaine
-
Patent number: 9251054Abstract: A method, system and computer program product are provided for implementing enhanced reliability of memory subsystems utilizing a dual port Dynamic Random Access Memory (DRAM) configuration. The DRAM configuration includes a first buffer and a second buffer, each buffer including a validity counter. The validity counter for a receiving buffer is incremented as each respective data row from a transferring buffer is validated through Error Correction Code (ECC), Reliability, Availability, and Serviceability (RAS) logic and transferred to the receiving buffer, while the validity counter for the transferring buffer is decremented. Data are read from or written to either the first buffer or the second buffer based upon a respective count value of the validity counters.Type: GrantFiled: March 27, 2014Date of Patent: February 2, 2016Assignee: International Business Machines CorporationInventors: Edgar R. Cordero, Carlos A. Fernandez, Joab D. Henderson, Jeffrey A. Sabrowski, Anuwat Saetow, Saravanan Sethuraman
-
Patent number: 9252131Abstract: By arranging dies in a stack such that failed cores are aligned with adjacent good cores, fast connections between good cores and cache of failed cores can be implemented. Cache can be allocated according to a priority assigned to each good core, by latency between a requesting core and available cache, and/or by load on a core.Type: GrantFiled: October 10, 2013Date of Patent: February 2, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Edgar R. Cordero, Anand Haridass, Subrat K. Panda, Saravanan Sethuraman, Diyanesh Babu Chinnakkonda Vidyapoornachary
-
Publication number: 20160027494Abstract: A method and apparatus for refreshing a row of a memory device prior to a scheduled refresh. A memory array may include a plurality of memory cells. The memory array may be configured to be refreshed at a first refresh time interval. The memory device may also include an intermediate refresh circuit. The intermediate refresh circuit may be configured to detect a triggering event and request a refresh for a row of the memory array in response to detecting a triggering event.Type: ApplicationFiled: October 8, 2015Publication date: January 28, 2016Inventors: Edgar R. Cordero, Joab D. Henderson, Kyu-hyoun Kim, Jeffrey A. Sabrowski, Anuwat Saetow
-
Patent number: 9245604Abstract: A method and apparatus for refreshing a row of a memory device prior to a scheduled refresh. A memory array may include a plurality of memory cells. The memory array may be configured to be refreshed at a first refresh time interval. The memory device may also include an intermediate refresh circuit. The intermediate refresh circuit may be configured to detect a triggering event and request a refresh for a row of the memory array in response to detecting a triggering event.Type: GrantFiled: May 8, 2013Date of Patent: January 26, 2016Assignee: International Business Machines CorporationInventors: Edgar R. Cordero, Joab D. Henderson, Kyu-hyoun Kim, Jeffrey A. Sabrowski, Anuwat Saetow
-
Patent number: 9230687Abstract: A method, system and computer program product are provided for implementing ECC (Error Correction Codes) redundancy using reconfigurable logic blocks in a computer system. When a fail is detected when reading from memory, it is determined if the incorrect data is in the data or the ECC component of the data. When incorrect data is found in the ECC component of the data, and an actionable threshold is not reached, a predetermined Reliability, Availability, and Serviceability (RAS) action is taken. When the actionable threshold is reached with incorrect data identified in the ECC component of the data, an analysis process is performed to determine if the ECC logic is faulty. When a fail in the ECC logic is detected, the identified ECC failed logic is replaced with a spare block of logic.Type: GrantFiled: April 22, 2013Date of Patent: January 5, 2016Assignee: International Business Machines CorporationInventors: Edgar R. Cordero, Timothy J. Dell, Joab D. Henderson, Jeffrey A. Sabrowski, Anuwat Saetow, Saravanan Sethuraman
-
Patent number: 9224450Abstract: A method and apparatus for modifying a reference voltage between refreshes in a memory device are disclosed. The memory array may include a plurality of memory cells. The memory device may also include a sense amplifier. The sense amplifier may be configured to read data from the plurality of memory cells using a reference voltage. The memory device may also include a sense amplifier reference voltage modification circuit. The sense amplifier reference voltage modification circuit may be configured to detect a triggering event and modify the reference voltage in response to detecting a triggering event.Type: GrantFiled: May 8, 2013Date of Patent: December 29, 2015Assignee: International Business Machines CorporationInventors: Edgar R. Cordero, Joab D. Henderson, Kyu-hyoun Kim, Jeffrey A. Sabrowski, Anuwat Saetow
-
Publication number: 20150370706Abstract: Apparatus and methods are disclosed that enable the allocation of a cache portion of a memory buffer to be utilized by an on-cache function controller (OFC) to execute processing functions on “main line” data. A particular method may include receiving, at a memory buffer, a request from a memory controller for allocation of a cache portion of the memory buffer. The method may also include acquiring, by an on-cache function controller (OFC) of the memory buffer, the requested cache portion of the memory buffer. The method may further include executing, by the OFC, a processing function on data stored at the cache portion of the memory buffer.Type: ApplicationFiled: June 18, 2014Publication date: December 24, 2015Inventors: Edgar R. Cordero, David M. Daly, Robert K. Montoye, Saravanan Sethuraman, Diyanesh B. Chinnakkonda Vidyapoornachary