Patents by Inventor Edgar R. Cordero
Edgar R. Cordero has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20150370711Abstract: Apparatus and methods are disclosed that enable the allocation of a cache portion of a memory buffer to be utilized by an on-cache function controller (OFC) to execute processing functions on “main line” data. A particular method may include receiving, at a memory buffer, a request from a memory controller for allocation of a cache portion of the memory buffer. The method may also include acquiring, by an on-cache function controller (OFC) of the memory buffer, the requested cache portion of the memory buffer. The method may further include executing, by the OFC, a processing function on data stored at the cache portion of the memory buffer.Type: ApplicationFiled: December 17, 2014Publication date: December 24, 2015Inventors: Edgar R. Cordero, David M. Daly, Robert K. Montoye, Saravanan Sethuraman, Diyanesh B. Chinnakkonda Vidyapoornachary
-
Publication number: 20150356004Abstract: In an example, an apparatus includes a memory controller. The memory controller may be configured to communicate a request to a computer program for a resource, to initialize a memory, and to perform operations on the memory as instructed. The computer program may be configured to make resources available in response to requests for the resources. The memory controller may be further configured to use the resource in response to an indication from the computer program that the resource is available.Type: ApplicationFiled: August 21, 2015Publication date: December 10, 2015Inventors: Edgar R. Cordero, Varkey K. Varghese, Diyanesh B. Vidyapoornachary
-
Publication number: 20150277542Abstract: According to embodiments of the disclosure, methods, systems and computer program products for memory power management and data consolidation are disclosed. The method may include selecting a first real memory portion and a second real memory portion from a plurality of real memory portions coupled to a memory controller in a computer system by a memory bus. The first real memory portion may be connected to a first buffer and the second real memory portion may be connected to a second buffer. The first and second real memory portions may be selected by the memory controller. The method may include migrating data from the first real memory portion to the second real memory portion on a migration bus through the first and second buffers. The method may also include placing the first real memory portion into a reduced power mode.Type: ApplicationFiled: March 28, 2014Publication date: October 1, 2015Applicant: International Business Machines CorporationInventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Edgar R. Cordero, Anand Haridass, Arun Joseph
-
Publication number: 20150278086Abstract: A method, system and computer program product are provided for implementing enhanced reliability of memory subsystems utilizing a dual port Dynamic Random Access Memory (DRAM) configuration. The DRAM configuration includes a first buffer and a second buffer, each buffer including a validity counter. The validity counter for a receiving buffer is incremented as each respective data row from a transferring buffer is validated through Error Correction Code (ECC), Reliability, Availability, and Serviceability (RAS) logic and transferred to the receiving buffer, while the validity counter for the transferring buffer is decremented. Data are read from or written to either the first buffer or the second buffer based upon a respective count value of the validity counters.Type: ApplicationFiled: March 27, 2014Publication date: October 1, 2015Applicant: International Business Machines CorporationInventors: Edgar R. Cordero, Carlos A. Fernandez, Joab D. Henderson, Jeffrey A. Sabrowski, Anuwat Saetow, Saravanan Sethuraman
-
Publication number: 20150277543Abstract: According to embodiments of the disclosure, methods, systems and computer program products for memory power management and data consolidation are disclosed. The method may include selecting a first real memory portion and a second real memory portion from a plurality of real memory portions coupled to a memory controller in a computer system by a memory bus. The first real memory portion may be connected to a first buffer and the second real memory portion may be connected to a second buffer. The first and second real memory portions may be selected by the memory controller. The method may include migrating data from the first real memory portion to the second real memory portion on a migration bus through the first and second buffers. The method may also include placing the first real memory portion into a reduced power mode.Type: ApplicationFiled: May 16, 2014Publication date: October 1, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Edgar R. Cordero, Anand Haridass, Arun Joseph
-
Publication number: 20150278005Abstract: A method, system and computer program product are provided for implementing enhanced reliability of memory subsystems utilizing a dual port Dynamic Random Access Memory (DRAM) configuration. The DRAM configuration includes a first buffer and a second buffer, each buffer including a validity counter. The validity counter for a receiving buffer is incremented as each respective data row from a transferring buffer is validated through Error Correction Code (ECC), Reliability, Availability, and Serviceability (RAS) logic and transferred to the receiving buffer, while the validity counter for the transferring buffer is decremented. Data are read from or written to either the first buffer or the second buffer based upon a respective count value of the validity counters.Type: ApplicationFiled: June 23, 2014Publication date: October 1, 2015Inventors: Edgar R. Cordero, Carlos A. Fernandez, Joab D. Henderson, Jeffrey A. Sabrowski, Anuwat Saetow, Saravanan Sethuraman
-
Patent number: 9147499Abstract: A method and apparatus for operation of a memory module for storage of a data word is provided. The apparatus includes a memory module having a set of paired memory devices including a first memory device to store a first section of a data word and a second memory device to store a second section of the data word when used in failure free operation. The apparatus may further include a first logic module to perform a write operation by writing the first and second sections of the data word to both the first memory device and the second memory device upon the determination of certain types of failure. The determination may include that a failure exists in the word section storage of either the first or second memory devices but that no failures exist in equivalent locations of word section storage in the two memory devices.Type: GrantFiled: February 18, 2013Date of Patent: September 29, 2015Assignee: International Business Machines CorporationInventors: Edgar R. Cordero, Timothy J. Dell, Girisankar Paulraj, Saravanan Sethuraman
-
Publication number: 20150269096Abstract: A first memory buffer has a first high speed memory channel and a second high speed memory channel. A second memory buffer is connected to the first memory buffer through a first connection. The second memory buffer has a third high speed memory channel and a fourth high speed memory channel. The first connection connects the first high speed memory channel and the third high speed memory channel. A first memory controller is connected to the first memory buffer through the second high speed memory channel. A second memory controller is connected to the second memory buffer through a second connection. The second connection is connected to the second memory buffer through the fourth high speed memory channel. A first memory module set is connected to the first memory buffer and a second memory module set is connected to the second memory buffer.Type: ApplicationFiled: March 20, 2014Publication date: September 24, 2015Applicant: International Business Machines CorporationInventors: Edgar R. Cordero, Girisankar Paulraj, Diyanesh B. Chinnakkonda Vidyapoornachary
-
Publication number: 20150268857Abstract: A first memory buffer has a first high speed memory channel and a second high speed memory channel. A second memory buffer is connected to the first memory buffer through a first connection. The second memory buffer has a third high speed memory channel and a fourth high speed memory channel. The first connection connects the first high speed memory channel and the third high speed memory channel. A first memory controller is connected to the first memory buffer through the second high speed memory channel. A second memory controller is connected to the second memory buffer through a second connection. The second connection is connected to the second memory buffer through the fourth high speed memory channel. A first memory module set is connected to the first memory buffer and a second memory module set is connected to the second memory buffer.Type: ApplicationFiled: April 7, 2014Publication date: September 24, 2015Applicant: International Business Machines CorporationInventors: Edgar R. Cordero, Girisankar Paulraj, Diyanesh B. Chinnakkonda Vidyapoornachary
-
Publication number: 20150228328Abstract: A method and apparatus for modifying a reference voltage between refreshes in a memory device are disclosed. The memory array may include a plurality of memory cells. The memory device may also include a sense amplifier. The sense amplifier may be configured to read data from the plurality of memory cells using a reference voltage. The memory device may also include a sense amplifier reference voltage modification circuit. The sense amplifier reference voltage modification circuit may be configured to detect a triggering event and modify the reference voltage in response to detecting a triggering event.Type: ApplicationFiled: April 23, 2015Publication date: August 13, 2015Inventors: Edgar R. Cordero, Joab D. Henderson, Kyu-hyoun Kim, Jeffrey A. Sabrowski, Anuwat Saetow
-
Publication number: 20150213854Abstract: A method, system and memory controller are provided for implementing simultaneous read and write operations in a memory subsystem utilizing a dual port Dynamic Random Access Memory (DRAM) configuration. A DRAM includes a first partition and a second partition. A memory controller determines if memory requirements are above or below a usage threshold. If the memory requirements are below the usage threshold, the memory is partitioned into a read buffer and a write buffer, with writes going to the write buffer and reads coming from the read buffer, data being transferred from the write buffer to the read buffer through an Error Correction Code (ECC) engine. If the memory requirements are above the usage threshold, the entire memory is used for reads and writes.Type: ApplicationFiled: June 20, 2014Publication date: July 30, 2015Inventors: Edgar R. Cordero, Carlos A. Fernandez, Joab D. Henderson, Jeffrey A. Sabrowski, Anuwat Saetow, Saravanan Sethuraman
-
Publication number: 20150213853Abstract: A method, system and memory controller are provided for implementing simultaneous read and write operations in a memory subsystem utilizing a dual port Dynamic Random Access Memory (DRAM) configuration. A DRAM includes a first partition and a second partition. A memory controller determines if memory requirements are above or below a usage threshold. If the memory requirements are below the usage threshold, the memory is partitioned into a read buffer and a write buffer, with writes going to the write buffer and reads coming from the read buffer, data being transferred from the write buffer to the read buffer through an Error Correction Code (ECC) engine. If the memory requirements are above the usage threshold, the entire memory is used for reads and writes.Type: ApplicationFiled: January 30, 2014Publication date: July 30, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Edgar R. Cordero, Carlos A. Fernandez, Joab D. Henderson, Jeffrey A. Sabrowski, Anuwat Saetow, Saravanan Sethuraman
-
Patent number: 9087615Abstract: A method for testing and correcting a memory system is described. The method includes selecting a target memory unit of the memory system having a timing margin in response to a trigger to start a timing margin measurement. The stored data in the target memory unit is moved to a spare memory unit. The memory system performs reads and writes of user data from the spare memory unit while measuring the target memory unit. The timing margins of the target memory unit are measured. The reliability of the measured timing margins of the target memory unit based on a timing margin profile is determined.Type: GrantFiled: May 3, 2013Date of Patent: July 21, 2015Assignee: International Business Machines CorporationInventors: Edgar R. Cordero, Timothy J. Dell, Anil B. Lingambudi, Diyanesh B. Vidyapoornachary
-
Patent number: 9086957Abstract: Systems and methods are provided to process a request for a memory space from a memory controller. A particular method may include communicating, by a memory controller, a request for a memory space of a memory to a computer program. The memory controller is configured to initialize the memory, and the memory controller is configured to perform operations on the memory as instructed. The computer program is configured to make memory spaces of the memory available in response to requests for the memory spaces of the memory. The method may also include using, by the memory controller, the memory space in response to an indication from the computer program that the memory space is available. Also provided are systems and methods for copying a memory space by a memory controller to a memory space under exclusive control of the memory controller.Type: GrantFiled: August 2, 2012Date of Patent: July 21, 2015Assignee: International Business Machines CorporationInventors: Edgar R. Cordero, Robert B. Tremaine, Varkey Kalloorthazchayil Varghese, Diyanesh B. Vidyapoornachary
-
Publication number: 20150178147Abstract: Exemplary embodiments of the present invention disclose a method and system for monitoring a first Error Correcting Code (ECC) device for failure and replacing the first ECC device with a second ECC device if the first ECC device begins to fail or fails. In a step, an exemplary embodiment performs a loopback test on an ECC device if a specified number of correctable errors is exceeded or if an uncorrectable error occurs. In another step, an exemplary embodiment replaces an ECC device that fails the loopback test with an ECC device that passes a loopback test.Type: ApplicationFiled: February 17, 2015Publication date: June 25, 2015Inventors: Edgar R. Cordero, Timothy J. Dell, Joab D. Henderson, Jeffrey A. Sabrowski, Anuwat Saetow, Saravanan Sethuraman
-
Patent number: 9063902Abstract: A method, system and computer program product are provided for implementing hardware assisted Dynamic Random Access Memory (DRAM) repair in a computer system that supports ECC. A data register providing DRAM repair is selectively provided in one of the Dynamic Random Access Memory (DRAM), a memory controller, or a memory buffer coupled between the DRAM and the memory controller. The data register is configured to map to any address. Responsive to the configured address being detected, the reads to or the writes from the configured address are routed to the data register.Type: GrantFiled: January 5, 2012Date of Patent: June 23, 2015Assignee: International Business Machines CorporationInventors: Edgar R. Cordero, Joab D. Henderson, Divya Kumar, Jeffrey A. Sabrowski, Anuwat Saetow
-
Patent number: 9052840Abstract: An apparatus and method is provided for coupling additional memory to a plurality of processors. The method may include determining the memory requirements of the plurality of processors in a system, comparing the memory requirements of the plurality of processors to an available memory assigned to each of the plurality of processors, and selecting a processor from the plurality of processors that requires additional memory capacity. The apparatus may include a plurality of processors, where the plurality of processors is coupled to a logic element. In addition, the apparatus may include an additional memory coupled to the logic element, where the logic element is adapted to select a processor from the plurality of processors to couple with the additional memory.Type: GrantFiled: March 1, 2013Date of Patent: June 9, 2015Assignee: International Business Machines CorporationInventors: Edgar R. Cordero, Anand Haridass, Diyanesh B. Vidyapoornachary, Robert B. Tremaine
-
Patent number: 9047057Abstract: An apparatus and method is provided for coupling additional memory to a plurality of processors. The method may include determining the memory requirements of the plurality of processors in a system, comparing the memory requirements of the plurality of processors to an available memory assigned to each of the plurality of processors, and selecting a processor from the plurality of processors that requires additional memory capacity. The apparatus may include a plurality of processors, where the plurality of processors is coupled to a logic element. In addition, the apparatus may include an additional memory coupled to the logic element, where the logic element is adapted to select a processor from the plurality of processors to couple with the additional memory.Type: GrantFiled: November 16, 2012Date of Patent: June 2, 2015Assignee: International Business Machines CorporationInventors: Edgar R. Cordero, Anand Haridass, Diyanesh B. Vidyapoornachary, Robert B. Tremaine
-
Patent number: 9037948Abstract: According to one embodiment, a method for error correction in a memory module having ranks is provided where each rank has memory devices. The method includes determining a first mark condition for a first rank of the memory module, the first mark condition based on one or more uncorrectable error occurring in a first memory device in the first rank, placing a first mark in the first memory device, determining a second mark condition for the first rank, the second mark condition based on one or more uncorrectable error occurring in a second memory device in the first rank, placing a second mark in a third memory device in a second rank of the memory module and configuring the first memory device to respond to commands directed to the second rank, wherein configuring the first memory device is based on placing of the first mark and the second mark.Type: GrantFiled: March 13, 2013Date of Patent: May 19, 2015Assignee: International Business Machines CorporationInventors: Edgar R. Cordero, Marc A. Gollub, Girisankar Paulraj, Diyanesh B. Vidyapoornachary
-
Publication number: 20150127898Abstract: A refresh command is communicated to a memory device to initiate an interruptible refresh which contains multiple segment refreshes separated by interrupt boundaries. A command is communicated to the memory device before execution of a segment refresh and the segment refresh is delayed at an interrupt boundary. Alternatively, a first number of commands in a queue is determined. A first number of segment refreshes to execute is determined based on the first number of commands. The first number of segment refreshes to execute is communicated to the memory device to cause execution of the first number of segment refreshes. A second number of commands in the queue is determined. A second number of segment refreshes to execute is determined based on the second number of commands. The second number of segment refreshes to execute is communicated to the memory device to cause execution of the second number of segment refreshes.Type: ApplicationFiled: November 7, 2013Publication date: May 7, 2015Applicant: International Business Machines CorporationInventors: Edgar R. Cordero, Carlos A. Fernandez, Joab D. Henderson, William P. Hovis, Jeffrey A. Sabrowski, Anuwat Saetow, Saravanan Sethuraman