Abstract: Various embodiments are provided herein for clearing memory of system in a computing environment. A zero-filled cache line with a single z-bit per entry in the cache directory may be defined. The “z” is a positive integer. A plurality of instruction set architecture (“ISA”) instructions are provided with a single z-bit in a cache line as defined in a cache directory to clear an entire cache line.

Abstract: Aspects of the invention include determining, by a machine learning model, a predicted workload for a system and a current system state of the system, determining an action to be enacted for the system based at least in part on the predicted workload and the current system state, enacting the action for the system, evaluating a state of the system after the action has been enacted, determining a reward for the machine learning model based at least in part on the state of the system after the action has been enacted, and updating the machine learning model based on the reward.

Abstract: Operating system deactivation of write protection for a storage block is provided absent quiescing of processors in a multi-processor computing environment. The process includes receiving an address translation protection exception interrupt resulting from an attempted write access by a processor to a storage block, and determining by the operating system whether write protection for the storage block is active. Based on write protection for the storage block not being active, the operating system issues an instruction to clear or modify translation lookaside buffer entries of the processor associated with the storage block, absent waiting for an action by another processor of multiple processors of the computing environment, to facilitate write access to the storage block proceeding at the processor.

Abstract: Operating system deactivation of write protection for a storage block is provided absent quiescing of processors in a multi-processor computing environment. The process includes receiving an address translation protection exception interrupt resulting from an attempted write access by a processor to a storage block, and determining by the operating system whether write protection for the storage block is active. Based on write protection for the storage block not being active, the operating system issues an instruction to clear or modify translation lookaside buffer entries of the processor associated with the storage block, absent waiting for an action by another processor of multiple processors of the computing environment, to facilitate write access to the storage block proceeding at the processor.

Abstract: An instruction is provided to perform a reset address translation protection operation when executed. Executing the instruction includes determining, by a processor, that an address translation protection bit in a specified translation table entry associated with a storage block is to be reset. Based on determining that the address translation protection bit is to be reset, executing the instruction includes resetting the address translation protection bit to deactivate write protection for the storage block. The resetting is absent waiting for an action by one or more other processors of the computing environment.

Abstract: Method and system are provided for running a smaller memory-address width program in a larger memory-address width address space. The method includes: dividing a smaller memory-address width program executable code into a set of portions; reserving a first virtual storage area in a part of an address space accessed using a smaller memory-address width address; and reserving a set of second virtual storage areas in a part of the address space accessed using a larger memory-address width address to accommodate the program executable code. The method provides a relocation mechanism to relocate a processor thread by translating using a relocation factor from an address in the reserved first virtual storage area to the one of the reserved second virtual storage areas containing the executable code.

Abstract: An aspect includes determining, via a processor, context attributes of a storage. Data address translation (DAT) tables are created, via the processor, to map virtual addresses to real addresses within the storage. When detecting, via the processor, that a context attribute of the storage has changed, and the DAT tables are updated based at least in part on the changed context attributes of the storage.

Abstract: A single architected instruction to perform multiple functions is executed. The executing includes performing a first function of the multiple functions and a second function of the multiple functions. The first function includes moving a block of data from one location to another location, and the second function includes setting one portion of a storage key using one selected key and another portion of the storage key using another selected key. The storage key is associated with the block of data and controls access to the block of data. The first function and the second function are performed as part of the single architected instruction.

Abstract: Interrupt code conversion for efficient computer program recovery. In response to an error being detected while processing instructions of a computer program running on a computer system, the OS receives a first program interrupt code (PIC) and interrupts the computer program. Control of the computer program is passed to a program interrupt handler and the program interrupt handler inspects the first PIC issued as a result of detecting the error. The first PIC is converted to a second PIC wherein the second PIC is associated with another error predicted when subsequent running of the computer program occurs. The second PIC is presented to a recovery routine associated with the computer program and, in response to the detected error, running of the computer program is customized based on the second PIC rather than the first PIC.

Abstract: A non-limiting example computer-implemented method includes receiving instructions to switch an operational context of a dynamic address translation (DAT) structure to a new operational context. It is determined if context switching has been enabled within the DAT structure. Based on determining that context switching is enabled, it is determined if the new operational context of the DAT structure is different than a current operational context of the DAT structure. It is chosen whether to switch to a full operational context based on the new operational context being different than the current operational context. If the full operational context is used, a full space DAT structure is set up and a private space bit is set to OFF, and if the full operational context is not used, a partial space DAT structure is set up and the private space bit is set to ON.

Abstract: An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.

Abstract: A single architected instruction to perform multiple functions is executed. The executing includes performing a first function of the multiple functions and a second function of the multiple functions. The first function includes moving a block of data from one location to another location, and the second function includes setting one portion of a storage key using one selected key and another portion of the storage key using another selected key. The storage key is associated with the block of data and controls access to the block of data. The first function and the second function are performed as part of the single architected instruction.

Abstract: Aspects of the invention include determining, by a machine learning model, a predicted workload for a system and a current system state of the system, determining an action to be enacted for the system based at least in part on the predicted workload and the current system state, enacting the action for the system, evaluating a state of the system after the action has been enacted, determining a reward for the machine learning model based at least in part on the state of the system after the action has been enacted, and updating the machine learning model based on the reward.

Abstract: A computer-implemented method for switching between a full space and a subspace across multiple address spaces is described. A non-limiting example of the computer-implemented method includes determining, by a processor, that switching between the full space and the subspace is enabled by examining a bit in a control register. The method determines, by the processor, that there is a new context different from an existing context based on the bit in the control register indicating that switching is enabled and switches, by the processor, the context of the multiple spaces based on determining that the new context is different from the existing context.

Abstract: An aspect includes determining, via a processor, context attributes of a storage. Data address translation (DAT) tables are created, via the processor, to map virtual addresses to real addresses within the storage. When detecting, via the processor, that a context attribute of the storage has changed, and the DAT tables are updated based at least in part on the changed context attributes of the storage.

Abstract: Examples of techniques for sensitive data redaction in a memory dump are described herein. An aspect includes, based on a dump of a virtual address space being triggered, receiving a primary dump corresponding to the virtual address space, the primary dump including one or more tagged memory pages. Another aspect includes identifying, by a sensitive data identification module, sensitive data that is located outside of the of the one or more tagged memory pages in the primary dump. Another aspect includes redacting data corresponding to the sensitive data and the one or more tagged memory pages to determine a redacted dump.

Abstract: A computer-implemented method for implementing a full space dynamic address translation (“DAT”) structure and a subspace DAT structure is provided. A non-limiting example of the computer-implemented method includes determining, by a processor, that switching between the full space DAT structure and the subspace DAT structure is enabled by examining a bit in a control register. The method determines, by the processor, that there is a new context different from an existing context based on the bit in the control register indicating that switching is enabled, and switches, by the processor, the context of the DAT structures based on determining that the new context is different from the existing context.

Abstract: Technical solutions are described for reducing page invalidation broadcasts in a computer system. An example method includes pre-allocating a pool of large memory frames by a real storage manager. The method also includes receiving, by a virtual storage manager, an instruction from an application to allocate a memory buffer, where the instruction includes a request to back the memory buffer using large pages. The virtual storage manager, in response to the instruction, allocates the memory buffer from the pre-allocated pool of large memory frames.

Abstract: Examples of techniques for memory tagging for sensitive data redaction in a memory dump are described herein. An aspect includes receiving a first call to a memory tagging application programming interface (API) from an application, wherein the first call designates a virtual memory page belonging to the application as containing sensitive data. Another aspect includes, based on the first call to the memory tagging API, tagging a physical memory page corresponding to the virtual memory page as sensitive.

Abstract: Examples of techniques for sensitive data redaction in a memory dump are described herein. An aspect includes, based on a dump of a virtual address space being triggered, receiving a primary dump corresponding to the virtual address space, the primary dump including one or more tagged memory pages. Another aspect includes identifying, by a sensitive data identification module, sensitive data that is located outside of the of the one or more tagged memory pages in the primary dump. Another aspect includes redacting data corresponding to the sensitive data and the one or more tagged memory pages to determine a redacted dump.