Patents by Inventor Elpida Tzortzatos

Elpida Tzortzatos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190146916
    Abstract: A shared cache line is concurrently modified by multiple processors of a computing environment. The concurrent modification is performed based, at least, on receiving one or more architected instructions (Fetch due to Non-Coherent Store instructions) that permit multiple processors to concurrently update the shared cache line absent obtaining a lock or having exclusive ownership of the data.
    Type: Application
    Filed: November 10, 2017
    Publication date: May 16, 2019
    Inventors: Nicholas C. Matsakis, Craig R. Walters, Jane H. Bartik, Chung-Lung K. Shum, Elpida Tzortzatos
  • Patent number: 10254962
    Abstract: In one embodiment, a computer-implemented method includes producing one or more clean frames by clearing a batch of one or more frames for use in backing virtual memory pages. The producing the one or more clean frames may be performed asynchronously from a unit of work being performed by a processor. The one or more clean frames may be added to a clean frame queue, where the clean frame queue includes a plurality of clean frames that have been cleared. A first request may be received, from the processor, for a frame for use in backing a virtual memory page of the unit of work. A clean frame, of the one or more clean frames, may be removed from the clean frame queue, responsive to the first request. The clean frame may be delivered to the processor, responsive to the first request.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: April 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert Miller, Jr., Steven M. Partlow, Thomas F. Rankin, Scott B. Tuttle, Elpida Tzortzatos
  • Patent number: 10216518
    Abstract: Embodiments of the present invention provide systems and methods for clearing specified blocks of main storage. In one embodiment, an EADM start subchannel is executed. The instructions of the execution of the EADM start subchannel may include a SAP receiving an ADM request block, which specifies a main-storage-clearing operation command. The address and size of a block of main memory to be cleared by the SAP is specified in an MSB designated by the ADM request block.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: February 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Anthony F. Coneski, Beth A. Glendening, Dan F. Greiner, Peter G. Sutton, Scott B. Tuttle, Elpida Tzortzatos
  • Patent number: 10216517
    Abstract: Embodiments of the present invention provide systems and methods for clearing specified blocks of main storage. In one embodiment, an EADM start subchannel is executed. The instructions of the execution of the EADM start subchannel may include a SAP receiving an ADM request block, which specifies a main-storage-clearing operation command. The address and size of a block of main memory to be cleared by the SAP is specified in an MSB designated by the ADM request block.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: February 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Anthony F. Coneski, Beth A. Glendening, Dan F. Greiner, Peter G. Sutton, Scott B. Tuttle, Elpida Tzortzatos
  • Patent number: 10168960
    Abstract: Technical solutions for reducing page invalidation broadcasts in virtual storage management are described. One general aspect includes a method including allocating, by a storage manager, a virtual memory page to a memory buffer that is used by an application being executed by a multiprocessor system, the virtual memory page being allocated from an address space of the application. The method also includes recording, by a memory management unit, a mapping between the virtual memory page and a physical location in a memory. The method also includes in response to a request, from the application, to deallocate the memory buffer, delaying invalidation of the mapping between the virtual memory page and the physical location in a memory, based on a count of free frames in the address space of the application.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert Miller, Jr., Harris M. Morgenstern, James H. Mulder, Elpida Tzortzatos, Dieter Wellerdiek
  • Publication number: 20180314557
    Abstract: A method, a computer program product, and a system for performing a batch processing are provided. The batch processing includes initializing a set of elements corresponding to a set of resources to produce an initialized group and chaining the initialized group to previously initialized elements to produce an element batch, when the previously initialized elements are available. The batch processing further includes setting a system lock on the set of resources after the element batch is produced; executing a service routine to move the element batch to a queue by referencing first and last elements of the element batch; and releasing the system lock on the set of resources once the service routine is complete.
    Type: Application
    Filed: September 4, 2015
    Publication date: November 1, 2018
    Inventors: David Hom, Charles E. Mari, Robert J. Miller, JR., Harris M. Morgenstern, Elpida Tzortzatos
  • Patent number: 10114853
    Abstract: A method, a computer program product, and a system for performing a batch processing are provided. The batch processing includes initializing a set of elements corresponding to a set of resources to produce an initialized group and chaining the initialized group to previously initialized elements to produce an element batch, when the previously initialized elements are available. The batch processing further includes setting a system lock on the set of resources after the element batch is produced; executing a service routine to move the element batch to a queue by referencing first and last elements of the element batch; and releasing the system lock on the set of resources once the service routine is complete.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: October 30, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David Hom, Charles E. Mari, Robert J. Miller, Jr., Harris M. Morgenstern, Elpida Tzortzatos
  • Publication number: 20180307618
    Abstract: A computer-implemented method includes pseudo-invalidating a first Dynamic Address Translation (DAT) table of a DAT structure associated with a workload. A page fault occurring during translation of a virtual memory address of data required by the workload is detected. Responsive to the page fault, the DAT structure is traversed. The DAT structure includes one or more DAT tables, and each DAT entry in each of the one or more DAT tables is associated with an in-use bit indicating whether the DAT entry is in use. Traversing the DAT structure includes pseudo-invalidating each of one or more DAT entries in the DAT structure that are involved in translating the virtual memory address for which the page fault occurred; and identifying a first page frame referenced by the virtual memory address for which the page fault occurred. The data in the first page frame is processed responsive to the page fault.
    Type: Application
    Filed: April 24, 2017
    Publication date: October 25, 2018
    Inventors: Charles E. Mari, Steven M. Partlow, Elpida Tzortzatos
  • Patent number: 10108466
    Abstract: A method, a computer program product, and a system for performing a batch processing are provided. The batch processing includes initializing a set of elements corresponding to a set of resources to produce an initialized group and chaining the initialized group to previously initialized elements to produce an element batch, when the previously initialized elements are available. The batch processing further includes setting a system lock on the set of resources after the element batch is produced; executing a service routine to move the element batch to a queue by referencing first and last elements of the element batch; and releasing the system lock on the set of resources once the service routine is complete.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: October 23, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David Hom, Charles E. Mari, Robert Miller, Jr., Harris M. Morgenstern, Elpida Tzortzatos
  • Publication number: 20180293153
    Abstract: An aspect includes generating instrumentation data for software that is executing on a computer and writing the instrumentation data to a memory located on the computer. An analytics application is provided with access to the instrumentation data. The writing the instrumentation data and the providing access are performed in real-time with respect to the generating. A request is received from the analytics application for at least a subset of the instrumentation data. Based on receiving the request, at least a subset of the instrumentation data is transmitted to the analytics application. A portion of the instrumentation data is migrated on a periodic basis to a non-volatile memory device that is external to the computer.
    Type: Application
    Filed: June 13, 2018
    Publication date: October 11, 2018
    Inventors: Theresa Y. Tai, Elpida Tzortzatos
  • Publication number: 20180275879
    Abstract: In one embodiment, a computer-implemented method includes producing one or more clean frames by clearing a batch of one or more frames for use in backing virtual memory pages. The producing the one or more clean frames may be performed asynchronously from a unit of work being performed by a processor. The one or more clean frames may be added to a clean frame queue, where the clean frame queue includes a plurality of clean frames that have been cleared. A first request may be received, from the processor, for a frame for use in backing a virtual memory page of the unit of work. A clean frame, of the one or more clean frames, may be removed from the clean frame queue, responsive to the first request. The clean frame may be delivered to the processor, responsive to the first request.
    Type: Application
    Filed: May 31, 2018
    Publication date: September 27, 2018
    Inventors: Robert Miller, JR., Steven M. Partlow, Thomas F. Rankin, Scott B. Tuttle, Elpida Tzortzatos
  • Publication number: 20180253245
    Abstract: A computer system includes memory and a processor configured to manage memory allocation. Aspects include receiving a request to execute a computer program and obtaining a learned data file for the computer program, the learned data file including a history of memory allocation requests and memory access requests by the computer program. Aspects also include receiving a memory allocation request from the computer program and allocating one or more pages of a virtual memory to the computer program, wherein a size of the one or more pages is based on the learned data file. Aspects further include backing at least one of the one or more pages of the virtual memory in the real memory prior to receiving an access request for the at least one of the one or more pages based on the learned data file.
    Type: Application
    Filed: March 6, 2017
    Publication date: September 6, 2018
    Inventors: Joseph W. GENTILE, Nicholas C. MATSAKIS, Elpida TZORTZATOS
  • Patent number: 10061518
    Abstract: In one embodiment, a computer-implemented method includes building an available frame header queue (AFHQ). The AFHQ includes one or more headers, each header including one or more frame references being no more than a maximum count of frame references. Each of the one or more frame references of each of the one or more headers refers to an available frame. A frame request is received for one or more requested frames. One or more frame references are extracted, by a computer processor, from the AFHQ in response to the frame request. The extracting includes extracting from the AFHQ one or more requested headers including the one or more frame references referring to at least a portion of the one or more requested frames.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: August 28, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David Hom, Harris M. Morgenstern, Steven M. Partlow, Scott B. Tuttle, Elpida Tzortzatos
  • Patent number: 10042739
    Abstract: An aspect includes generating instrumentation data for software that is executing on a computer and writing the instrumentation data to a memory located on the computer. An analytics application is provided with access to the instrumentation data. The writing the instrumentation data and the providing access are performed in real-time with respect to the generating. A request is received from the analytics application for at least a subset of the instrumentation data. Based on receiving the request, at least a subset of the instrumentation data is transmitted to the analytics application. A portion of the instrumentation data is migrated on a periodic basis to a non-volatile memory device that is external to the computer.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: August 7, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Theresa Y. Tai, Elpida Tzortzatos
  • Patent number: 10031694
    Abstract: In one embodiment, a computer-implemented method includes producing one or more clean frames by clearing a batch of one or more frames for use in backing virtual memory pages. The producing the one or more clean frames may be performed asynchronously from a unit of work being performed by a processor. The one or more clean frames may be added to a clean frame queue, where the clean frame queue includes a plurality of clean frames that have been cleared. A first request may be received, from the processor, for a frame for use in backing a virtual memory page of the unit of work. A clean frame, of the one or more clean frames, may be removed from the clean frame queue, responsive to the first request. The clean frame may be delivered to the processor, responsive to the first request.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: July 24, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert Miller, Jr., Steven M. Partlow, Thomas F. Rankin, Scott B. Tuttle, Elpida Tzortzatos
  • Patent number: 9996349
    Abstract: Embodiments of the present invention provide systems and methods for clearing specified blocks of main storage. In one embodiment, an EADM start subchannel is executed. The instructions of the execution of the EADM start subchannel may include a SAP receiving an ADM request block, which specifies a main-storage-clearing operation command. The address and size of a block of main memory to be cleared by the SAP is specified in an MSB designated by the ADM request block.
    Type: Grant
    Filed: January 27, 2015
    Date of Patent: June 12, 2018
    Assignee: International Business Machines Corporation
    Inventors: Anthony F. Coneski, Beth A. Glendening, Dan F. Greiner, Peter G. Sutton, Scott B. Tuttle, Elpida Tzortzatos
  • Publication number: 20180088868
    Abstract: Technical solutions for reducing page invalidation broadcasts in virtual storage management are described. One general aspect includes a method including allocating, by a storage manager, a virtual memory page to a memory buffer that is used by an application being executed by a multiprocessor system, the virtual memory page being allocated from an address space of the application. The method also includes recording, by a memory management unit, a mapping between the virtual memory page and a physical location in a memory. The method also includes in response to a request, from the application, to deallocate the memory buffer, delaying invalidation of the mapping between the virtual memory page and the physical location in a memory, based on a count of free frames in the address space of the application.
    Type: Application
    Filed: November 14, 2017
    Publication date: March 29, 2018
    Inventors: ROBERT MILLER, JR., HARRIS M. MORGENSTERN, JAMES H. MULDER, ELPIDA TZORTZATOS, DIETER WELLERDIEK
  • Publication number: 20180089062
    Abstract: An aspect includes generating instrumentation data for software that is executing on a computer and writing the instrumentation data to a memory located on the computer. An analytics application is provided with access to the instrumentation data. The writing the instrumentation data and the providing access are performed in real-time with respect to the generating. A request is received from the analytics application for at least a subset of the instrumentation data. Based on receiving the request, at least a subset of the instrumentation data is transmitted to the analytics application. A portion of the instrumentation data is migrated on a periodic basis to a non-volatile memory device that is external to the computer.
    Type: Application
    Filed: September 29, 2016
    Publication date: March 29, 2018
    Inventors: Theresa Y. Tai, Elpida Tzortzatos
  • Publication number: 20180074706
    Abstract: In one embodiment, a computer-implemented method includes building an available frame header queue (AFHQ). The AFHQ includes one or more headers, each header including one or more frame references being no more than a maximum count of frame references. Each of the one or more frame references of each of the one or more headers refers to an available frame. A frame request is received for one or more requested frames. One or more frame references are extracted, by a computer processor, from the AFHQ in response to the frame request. The extracting includes extracting from the AFHQ one or more requested headers including the one or more frame references referring to at least a portion of the one or more requested frames.
    Type: Application
    Filed: November 29, 2017
    Publication date: March 15, 2018
    Inventors: David Hom, Harris M. Morgenstern, Steven M. Partlow, Scott B. Tuttle, Elpida Tzortzatos
  • Publication number: 20180067682
    Abstract: Systems, methods, and computer-readable media are disclosed for providing a multi-tenant computing environment that allows an authorized user space application within a logical grouping of applications to utilize reserved hardware resources such as processor or memory resources in a manner that isolates the reserved hardware resources from hardware resources utilized by applications outside the logical grouping.
    Type: Application
    Filed: September 2, 2016
    Publication date: March 8, 2018
    Inventors: Anthony T. Sofia, Elpida Tzortzatos, Jessie Yu