Abstract: Examples of techniques for memory tagging for sensitive data redaction in a memory dump are described herein. An aspect includes receiving a first call to a memory tagging application programming interface (API) from an application, wherein the first call designates a virtual memory page belonging to the application as containing sensitive data.

Abstract: An aspect includes determining, via a processor, context attributes of a storage. Data address translation (DAT) tables are created, via the processor, to map virtual addresses to real addresses within the storage. When detecting, via the processor, that a context attribute of the storage has changed, and the DAT tables are updated based at least in part on the changed context attributes of the storage.

Abstract: Memory management is provided which includes a page replacement process managed by a storage manager and a workload manager. The page replacement process swaps out the content associated with a frame of physical memory to an auxiliary storage in order to provide a free frame. The memory management process includes: determining that the physical memory runs out of free frames; providing priority information from the workload manager to the storage manager, the priority information indicating the priority or business relevance of a certain process; selecting one or more pages to be swapped to the auxiliary storage based on the priority information; and swapping out the contents of the one or more selected pages to the auxiliary storage.

Abstract: A computer-implemented method for switching between a full space and a subspace across multiple address spaces is described. A non-limiting example of the computer-implemented method includes determining, by a processor, that switching between the full space and the subspace is enabled by examining a bit in a control register. The method determines, by the processor, that there is a new context different from an existing context based on the bit in the control register indicating that switching is enabled and switches, by the processor, the context of the multiple spaces based on determining that the new context is different from the existing context.

Abstract: An aspect includes determining, via a processor, context attributes of a storage. Data address translation (DAT) tables are created, via the processor, to map virtual addresses to real addresses within the storage. When detecting, via the processor, that a context attribute of the storage has changed, and the DAT tables are updated based at least in part on the changed context attributes of the storage.

Abstract: A non-limiting example computer-implemented method includes receiving instructions to switch an operational context of a dynamic address translation (DAT) structure to a new operational context. It is determined if context switching has been enabled within the DAT structure. Based on determining that context switching is enabled, it is determined if the new operational context of the DAT structure is different than a current operational context of the DAT structure. It is chosen whether to switch to a full operational context based on the new operational context being different than the current operational context. If the full operational context is used, a full space DAT structure is set up and a private space bit is set to OFF, and if the full operational context is not used, a partial space DAT structure is set up and the private space bit is set to ON.

Abstract: A computer-implemented method for implementing a full space dynamic address translation (“DAT”) structure and a subspace DAT structure is provided. A non-limiting example of the computer-implemented method includes determining, by a processor, that switching between the full space DAT structure and the subspace DAT structure is enabled by examining a bit in a control register. The method determines, by the processor, that there is a new context different from an existing context based on the bit in the control register indicating that switching is enabled, and switches, by the processor, the context of the DAT structures based on determining that the new context is different from the existing context.

Abstract: Interrupt code conversion for efficient computer program recovery. In response to an error being detected while processing instructions of a computer program running on a computer system, the OS receives a first program interrupt code (PIC) and interrupts the computer program. Control of the computer program is passed to a program interrupt handler and the program interrupt handler inspects the first PIC issued as a result of detecting the error. The first PIC is converted to a second PIC wherein the second PIC is associated with another error predicted when subsequent running of the computer program occurs. The second PIC is presented to a recovery routine associated with the computer program and, in response to the detected error, running of the computer program is customized based on the second PIC rather than the first PIC.

Abstract: A single architected instruction is obtained to perform multiple functions. The instruction is executed, and the executing includes performing a first function of the multiple functions and a second function of the multiple functions. The first function includes moving a block of data from one location to another location, and the second function includes setting a storage key. The storage key is associated with the block of data at the other location and controls access to the block of data. The first function and the second function are performed as part of the single architected instruction.

Abstract: A shared cache line is concurrently modified by multiple processors of a computing environment. The concurrent modification is performed based, at least, on receiving one or more architected instructions (Fetch due to Non-Coherent Store instructions) that permit multiple processors to concurrently update the shared cache line absent obtaining a lock or having exclusive ownership of the data.

Abstract: A single architected instruction is obtained to perform multiple functions. The instruction is executed, and the executing includes performing a first function of the multiple functions and a second function of the multiple functions. The first function includes moving a block of data from one location to another location, and the second function includes setting a storage key. The storage key is associated with the block of data at the other location and controls access to the block of data. The first function and the second function are performed as part of the single architected instruction.

Abstract: A single architected instruction to perform multiple functions is executed. The executing includes performing a first function of the multiple functions and a second function of the multiple functions. The first function includes moving a block of data from one location to another location, and the second function includes setting one portion of a storage key using one selected key and another portion of the storage key using another selected key. The storage key is associated with the block of data and controls access to the block of data. The first function and the second function are performed as part of the single architected instruction.

Abstract: Embodiments are provided for implementing a transparent conversion of common virtual storage requests to storage with limited access. Embodiments include providing a storage manager configured to perform address translation for requests, providing a data address translation (DAT) structure configured to connect a higher-level DAT table to a lower-level DAT table, and creating the DAT structure based on a request from a process. Embodiments also include responsive to receiving a storage request, performing a DAT fault process based on validating user credentials associated with an entry of the higher-level DAT table corresponding to the storage request, and responsive to the validation, updating the higher-level DAT table entry to allow access to the restricted-use portion of the common virtual storage, and otherwise, returning a DAT fault for the higher-level DAT table entry.

Abstract: An aspect includes generating instrumentation data for software that is executing on a computer and writing the instrumentation data to a memory located on the computer. An analytics application is provided with access to the instrumentation data. The writing the instrumentation data and the providing access are performed in real-time with respect to the generating. A request is received from the analytics application for at least a subset of the instrumentation data. Based on receiving the request, at least a subset of the instrumentation data is transmitted to the analytics application. A portion of the instrumentation data is migrated on a periodic basis to a non-volatile memory device that is external to the computer.

Abstract: A computer-implemented method includes pseudo-invalidating a first Dynamic Address Translation (DAT) table of a DAT structure associated with a workload. A page fault occurring during translation of a virtual memory address of data required by the workload is detected. Responsive to the page fault, the DAT structure is traversed. The DAT structure includes one or more DAT tables, and each DAT entry in each of the one or more DAT tables is associated with an in-use bit indicating whether the DAT entry is in use. Traversing the DAT structure includes pseudo-invalidating each of one or more DAT entries in the DAT structure that are involved in translating the virtual memory address for which the page fault occurred; and identifying a first page frame referenced by the virtual memory address for which the page fault occurred. The data in the first page frame is processed responsive to the page fault.

Abstract: An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.

Abstract: An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.

Abstract: A memory system is configured for access by a plurality of computer processing units. An address lock bit is configured in a translation table of the memory system. The address lock supports both address lock shared and address lock exclusive functions. A storage manager of an operating system configured to obtain exclusive access to an entry in a DAT table either by obtaining an address space lock exclusive or obtaining an address space lock shared, and setting a lock bit in a DAT entry.

Abstract: A method for obtaining and storing monitoring information. The method includes one or more computer processors generating a plurality of data records, based at least in part on a configuration for generating information, wherein the plurality of data records includes a first data record. The method further includes determining that a configuration for analyzing information dictates an analysis of at least a one data record, wherein the at least one data record includes a second data record. The method further includes determining that the plurality of data records do not include the second data record. The method further includes modifying the configuration for generating information to include generating the second data record. The method further includes generating an updated plurality of data records based on the modified configuration for generating information, wherein the updated plurality of data records includes the first data record and the second data record.

Abstract: A computer system includes memory and a processor configured to manage memory allocation. Aspects include receiving a request to execute a computer program and obtaining a learned data file for the computer program, the learned data file including a history of memory allocation requests and memory access requests by the computer program. Aspects also include receiving a memory allocation request from the computer program and allocating one or more pages of a virtual memory to the computer program, wherein a size of the one or more pages is based on the learned data file. Aspects further include backing at least one of the one or more pages of the virtual memory in the real memory prior to receiving an access request for the at least one of the one or more pages based on the learned data file.