Patents by Inventor Eric G. Stevens
Eric G. Stevens has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10388688Abstract: An image sensor with a pinned photodiode includes a photodiode formed in a substrate by implanting dopants of a first type through one or more dielectric layers formed over the substrate. A pinning layer for the photodiode may be formed by implanting dopants of a second type through the same one or more dielectric layers. The pinning layer may be formed over a photodiode region of the substrate. The concentration of dopants of the second type may have a maximum value in dielectric layers over the photodiode that exceeds the concentration of dopants of the second type in the substrate below. The photodiode and pinning layer may both be formed by implanting ions of the first and second type respectively through a dielectric layer formed after etching away a portion of another dielectric layer, having a different thickness, and having different optical transmission properties than the another dielectric layer.Type: GrantFiled: May 15, 2017Date of Patent: August 20, 2019Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Eric G. Stevens
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Patent number: 10341590Abstract: Various embodiments of the present technology may comprise methods and apparatus for a CCD image sensor. The image sensor may comprise a center channel disposed along a horizontal center line of the pixel array for collecting and transferring charge. The center channel is electrically coupled to a lateral overflow drain. In various embodiments, the image sensor may comprise a light shield under a gap between neighboring microlenses, such as a gap along the center line, to block light, such as to maintain a uniform, spatial sampling pattern across the device. In various embodiments, the image sensor may comprise a barrier region disposed between the center channel and the lateral overflow drain, for example to prevent charge from the lateral overflow drain being injected back into the center channel and adjacent pixels.Type: GrantFiled: August 12, 2016Date of Patent: July 2, 2019Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Shen Wang, Eric J. Meisenzahl, Eric G. Stevens
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Publication number: 20180048835Abstract: Various embodiments of the present technology may comprise methods and apparatus for a CCD image sensor. The image sensor may comprise a center channel disposed along a horizontal center line of the pixel array for collecting and transferring charge. The center channel is electrically coupled to a lateral overflow drain. In various embodiments, the image sensor may comprise a light shield under a gap between neighboring microlenses, such as a gap along the center line, to block light, such as to maintain a uniform, spatial sampling pattern across the device. In various embodiments, the image sensor may comprise a barrier region disposed between the center channel and the lateral overflow drain, for example to prevent charge from the lateral overflow drain being injected back into the center channel and adjacent pixels.Type: ApplicationFiled: August 12, 2016Publication date: February 15, 2018Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Shen WANG, Eric J. MEISENZAHL, Eric G. STEVENS
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Publication number: 20170250217Abstract: An image sensor with a pinned photodiode includes a photodiode formed in a substrate by implanting dopants of a first type through one or more dielectric layers formed over the substrate. A pinning layer for the photodiode may be formed by implanting dopants of a second type through the same one or more dielectric layers. The pinning layer may be formed over a photodiode region of the substrate. The concentration of dopants of the second type may have a maximum value in dielectric layers over the photodiode that exceeds the concentration of dopants of the second type in the substrate below. The photodiode and pinning layer may both be formed by implanting ions of the first and second type respectively through a dielectric layer formed after etching away a portion of another dielectric layer, having a different thickness, and having different optical transmission properties than the another dielectric layer.Type: ApplicationFiled: May 15, 2017Publication date: August 31, 2017Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Eric G. STEVENS
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Patent number: 9685479Abstract: An image sensor with a pinned photodiode includes a photodiode formed in a substrate by implanting dopants of a first type through one or more dielectric layers formed over the substrate. A pinning layer for the photodiode may be formed by implanting dopants of a second type through the same one or more dielectric layers. The pinning layer may be formed over a photodiode region of the substrate. The concentration of dopants of the second type may have a maximum value in dielectric layers over the photodiode that exceeds the concentration of dopants of the second type in the substrate below. The photodiode and pinning layer may both be formed by implanting ions of the first and second type respectively through a dielectric layer formed after etching away a portion of another dielectric layer, having a different thickness, and having different optical transmission properties than the another dielectric layer.Type: GrantFiled: March 31, 2015Date of Patent: June 20, 2017Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Eric G. Stevens
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Publication number: 20160293660Abstract: An image sensor with a pinned photodiode includes a photodiode formed in a substrate by implanting dopants of a first type through one or more dielectric layers formed over the substrate. A pinning layer for the photodiode may be formed by implanting dopants of a second type through the same one or more dielectric layers. The pinning layer may be formed over a photodiode region of the substrate. The concentration of dopants of the second type may have a maximum value in dielectric layers over the photodiode that exceeds the concentration of dopants of the second type in the substrate below. The photodiode and pinning layer may both be formed by implanting ions of the first and second type respectively through a dielectric layer formed after etching away a portion of another dielectric layer, having a different thickness, and having different optical transmission properties than the another dielectric layer.Type: ApplicationFiled: March 31, 2015Publication date: October 6, 2016Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Eric G. STEVENS
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Patent number: 9431456Abstract: An image sensor is fabricated by forming transfer gates over a substrate layer. A transfer gate is disposed between a respective shared charge-to-voltage conversion region and a photodetector associated with the shared charge-to-voltage conversion region. The transfer gates of each shared charge-to-voltage conversion region are spaced apart to form a conversion region gap. A masking conformal dielectric layer is deposited over the image sensor, covers the transfer gates, fills each conversion region gap, and is etched to form sidewall spacers along an outside edge of each transfer gate with a portion remaining in each conversion region gap and disposed over the substrate layer in each conversion region gap. Source/drain regions are implanted in the substrate layer where an implant region is formed in the transfer gates. The masking conformal dielectric layer in each conversion gap masks the source/drain implant Each charge-to-voltage conversion region is substantially devoid of the implant region.Type: GrantFiled: February 10, 2015Date of Patent: August 30, 2016Assignee: OmniVision Technologies, Inc.Inventors: Hung Q. Doan, Eric G. Stevens
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Publication number: 20150179701Abstract: An image sensor is fabricated by forming transfer gates over a substrate layer. A transfer gate is disposed between a respective shared charge-to-voltage conversion region and a photodetector associated with the shared charge-to-voltage conversion region. The transfer gates of each shared charge-to-voltage conversion region are spaced apart to form a conversion region gap. A masking conformal dielectric layer is deposited over the image sensor, covers the transfer gates, fills each conversion region gap, and is etched to form sidewall spacers along an outside edge of each transfer gate with a portion remaining in each conversion region gap and disposed over the substrate layer in each conversion region gap. Source/drain regions are implanted in the substrate layer where an implant region is formed in the transfer gates. The masking conformal dielectric layer in each conversion gap masks the source/drain implant Each charge-to-voltage conversion region is substantially devoid of the implant region.Type: ApplicationFiled: February 10, 2015Publication date: June 25, 2015Inventors: Hung Q. Doan, Eric G. Stevens
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Patent number: 9000500Abstract: An image sensor includes an array of pixels, with at least one pixel including a photodetector formed in a substrate layer and a transfer gate disposed adjacent to the photodetector. The substrate layer further includes multiple charge-to-voltage conversion regions. A single photodetector can transfer collected charge to a single charge-to-voltage conversion region, or alternatively multiple photodetectors can transfer collected charge to a common charge-to-voltage conversion region shared by the photodetectors. An implant region formed when dopants are implanted into the substrate layer to form source/drain implant regions is disposed in only a portion of each transfer gate while each charge-to-voltage conversion region is substantially devoid of the implant region.Type: GrantFiled: November 9, 2010Date of Patent: April 7, 2015Assignee: OmniVision Technologies, Inc.Inventors: Hung Q. Doan, Eric G. Stevens
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Patent number: 8994139Abstract: A lateral overflow drain and a channel stop are fabricated using a double mask process. Each lateral overflow drain is formed within a respective channel stop. Due to the use of two mask layers, one edge of each lateral overflow drain is aligned, or substantially aligned, with an edge of a respective channel stop.Type: GrantFiled: March 8, 2012Date of Patent: March 31, 2015Assignee: Semiconductor Components Industries, LLCInventors: Edmund K. Banghart, Eric G. Stevens, Hung Q. Doan
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Patent number: 8772891Abstract: A lateral overflow drain and a channel stop are fabricated using a double mask process. Each lateral overflow drain is formed within a respective channel stop. Due to the use of two mask layers, one edge of each lateral overflow drain is aligned, or substantially aligned, with an edge of a respective channel stop.Type: GrantFiled: October 30, 2009Date of Patent: July 8, 2014Assignee: Truesense Imaging, Inc.Inventors: Edmund K. Banghart, Eric G. Stevens, Hung Q. Doan
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Patent number: 8618458Abstract: A back-illuminated image sensor includes a sensor layer disposed between an insulating layer and a circuit layer electrically connected to the sensor layer. An imaging area includes a plurality of photodetectors is formed in the sensor layer and a well that spans the imaging area. The well can be disposed between the backside of the sensor layer and the photodetectors, or the well can be a buried well formed adjacent to the backside of the sensor layer with a region including formed between the photodetectors and the buried well. One or more side wells can be formed laterally adjacent to each photodetector. The dopant in the well has a segregation coefficient that causes the dopant to accumulate on the sensor layer side of an interface between the sensor layer and the insulating layer.Type: GrantFiled: November 7, 2008Date of Patent: December 31, 2013Assignee: OmniVision Technologies, Inc.Inventors: John P. McCarten, Joseph R. Summa, Cristian A. Tivarus, Todd J. Anderson, Eric G. Stevens
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Patent number: 8378398Abstract: Shallow trench isolation regions are disposed in an n-type silicon semiconductor layer laterally adjacent to a collection region of a photodetector and laterally adjacent to a charge-to-voltage conversion region. The shallow trench isolation regions each include a trench disposed in the silicon semiconductor layer and a first dielectric structure disposed along an interior bottom and sidewalls of each trench. A second dielectric structure is disposed over the pinning layer. The dielectric structures include a silicon nitride layer disposed over an oxide layer. An n-type isolation layer is disposed along only a portion of the exterior bottom of the trench and the exterior sidewall of the trench immediately adjacent to the photodetector. The n-type isolation layer is not disposed along the remaining portion of the bottom or the opposing exterior sidewall of the trench.Type: GrantFiled: December 13, 2010Date of Patent: February 19, 2013Assignee: OmniVision Technologies, Inc.Inventors: Hung Q. Doan, Eric G. Stevens, Robert M. Guidash
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Patent number: 8329499Abstract: A lateral overflow drain and a channel stop are fabricated using a double mask process. Each lateral overflow drain is formed within a respective channel stop. Due to the use of two mask layers, one edge of each lateral overflow drain is aligned, or substantially aligned, with an edge of a respective channel stop.Type: GrantFiled: October 30, 2009Date of Patent: December 11, 2012Assignee: Truesense Imaging, Inc.Inventors: Edmund K. Banghart, Eric G. Stevens, Hung Q. Doan
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Publication number: 20120168892Abstract: A lateral overflow drain and a channel stop are fabricated using a double mask process. Each lateral overflow drain is formed within a respective channel stop. Due to the use of two mask layers, one edge of each lateral overflow drain is aligned, or substantially aligned, with an edge of a respective channel stop.Type: ApplicationFiled: March 8, 2012Publication date: July 5, 2012Inventors: Edmund K. Banghart, Eric G. Stevens, Hung Q. Doan
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Publication number: 20120080731Abstract: A first shallow trench isolation region is disposed in the silicon semiconductor layer laterally adjacent to a photodetector while a second shallow trench isolation region is disposed in the silicon semiconductor layer laterally adjacent to other electrical components in a pixel. The first and second shallow trench isolation regions each include a trench disposed in the silicon semiconductor layer that is filled with a dielectric material. An isolation layer having the second conductivity is disposed only along a portion of a bottom and only along a sidewall of the trench immediately adjacent to the photodetector. The isolation layer is not disposed along the other portion of the bottom and along the other sidewall of the trench adjacent the photodetector. The isolation layer is not disposed along the bottom and sidewalls of the trench adjacent to the other electrical components.Type: ApplicationFiled: September 30, 2010Publication date: April 5, 2012Inventors: Hung Q. Doan, Eric G. Stevens, Robert M. Guidash
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Publication number: 20120083067Abstract: A first shallow trench isolation region is disposed in the silicon semiconductor layer laterally adjacent to a photodetector while a second shallow trench isolation region is disposed in the silicon semiconductor layer laterally adjacent to other electrical components in a pixel. The first and second shallow trench isolation regions each include a trench disposed in the silicon semiconductor layer that is filled with a dielectric material. An isolation layer having the second conductivity is disposed only along a portion of a bottom and only along a sidewall of the trench immediately adjacent to the photodetector. The isolation layer is not disposed along the other portion of the bottom and along the other sidewall of the trench adjacent the photodetector. The isolation layer is not disposed along the bottom and sidewalls of the trench adjacent to the other electrical components.Type: ApplicationFiled: September 30, 2010Publication date: April 5, 2012Inventors: Hung Q. Doan, Eric G. Stevens, Robert M. Guidash
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Publication number: 20120080733Abstract: Shallow trench isolation regions are disposed in an n-type silicon semiconductor layer laterally adjacent to a collection region of a photodetector and laterally adjacent to a charge-to-voltage conversion region. The shallow trench isolation regions each include a trench disposed in the silicon semiconductor layer and a first dielectric structure disposed along an interior bottom and sidewalls of each trench. A second dielectric structure is disposed over the pinning layer. The dielectric structures include a silicon nitride layer disposed over an oxide layer. An n-type isolation layer is disposed along only a portion of the exterior bottom of the trench and the exterior sidewall of the trench immediately adjacent to the photodetector. The n-type isolation layer is not disposed along the remaining portion of the bottom or the opposing exterior sidewall of the trench.Type: ApplicationFiled: December 13, 2010Publication date: April 5, 2012Inventors: Hung Q. Doan, Eric G. Stevens, Robert M. Guidash
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Patent number: 8101450Abstract: Shallow trench isolation regions are disposed in an n-type silicon semiconductor layer laterally adjacent to a collection region of a photodetector and laterally adjacent to a charge-to-voltage conversion region. The shallow trench isolation regions each include a trench disposed in the silicon semiconductor layer and a first dielectric structure disposed along an interior bottom and sidewalls of each trench. A second dielectric structure is disposed over the pinning layer. The dielectric structures include a silicon nitride layer disposed over an oxide layer. An n-type isolation layer is disposed along only a portion of the exterior bottom of the trench and the exterior sidewall of the trench immediately adjacent to the photodetector. The n-type isolation layer is not disposed along the remaining portion of the bottom or the opposing exterior sidewall of the trench.Type: GrantFiled: December 13, 2010Date of Patent: January 24, 2012Assignee: OmniVision Technologies, Inc.Inventors: Hung Q. Doan, Eric G. Stevens, Robert M. Guidash
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Patent number: 8076746Abstract: A back-illuminated image sensor includes a sensor layer of a first conductivity type having a frontside and a backside opposite the frontside. One or more frontside regions of a second conductivity type are formed in at least a portion of the frontside of the sensor layer. A backside region of the second conductivity type is formed in the backside of the sensor layer. A plurality of frontside photodetectors of the first conductivity type is disposed in the sensor layer. A distinct plurality of backside photodetectors of the first conductivity type separate from the plurality of frontside photodetectors are formed in the sensor layer contiguous to portions of the region of the second conductivity type. A voltage terminal is disposed on the frontside of the sensor layer. One or more connecting regions of the second conductivity type are disposed in respective portions of the sensor layer between the voltage terminal and the backside region for electrically connecting the voltage terminal to the backside region.Type: GrantFiled: June 26, 2009Date of Patent: December 13, 2011Assignee: OmniVision Technologies, Inc.Inventors: John P. McCarten, Cristian A. Tivarus, Joseph R. Summa, Eric G. Stevens, Hung Q. Doan, Robert M. Guidash