Abstract: The optimization of two technologies (CMOS and CCD) wherein a pinned photodiode is integrated into the image sensing element of an active pixel sensor. Pinned photodiodes are fabricated with CCD process steps into the active pixel architecture. Charge integrated within the active pixel pinned photodiode is transferred into the charge sensing node by a transfer gate. The floating diffusion is coupled CMOS circuitry that can provide the addressing capabilities of individual pixels. Alternatively, a buried channel photocapacitor can be used in place of the pinned photodiode.

Abstract: A self aligned, lateral-overflow drain antiblooming structure that is insensitive to drain bias voltages and therefore has improved insensitivity to process variations. The length of the antiblooming barrier regions are easily adjusted and determined by photolithography. The self aligned, lateral-overflow drain (LOD) antiblooming structure results in a design that saves space, and hence, improves overall sensor performance. In this structure, an antiblooming potential barrier is provided that is smaller (in volts) than the barriers that separate the pixels from one another so that excess charge will flow preferentially into the LOD as opposed to the adjacent pixels.

Abstract: The optimization of two technologies (CMOS and CCD) wherein a pinned photodiode is integrated into the image sensing element of an active pixel sensor. Pinned photodiodes are fabricated with CCD process steps into the active pixel architecture. Charge integrated within the active pixel pinned photodiode is transferred into the charge sensing node by a transfer gate. The floating diffusion is coupled CMOS circuitry that can provide the addressing capabilities of individual pixels. Alternatively, a buried channel photocapacitor can be used in place of the pinned photodiode.

Abstract: This invention concerns a novel structure to create a low capacitance floating diffusion without changing or adding steps to the image sensor fabrication process. It consists of incorporation of a novel structure at the contact area between the floating diffusion and the gate electrode that reduces the junction capacitance of the floating diffusion and improves the sensitivity of the device (the structure features overlapping contact, gate, metalization and n-type regions which provide the electrical contact between the floating diffusion and the gate). Additionally, the structure has a low resistance diffusion region that is self aligned with a gate electrode.

Abstract: A self aligned, lateral-overflow drain antiblooming structure that is insensitive to drain bias voltages and therefore has improved insensitivity to process variations. The length of the antiblooming barrier regions are easily adjusted and determined by photolithography. The self aligned, lateral-overflow drain (LOD) antiblooming structure results in a design that saves space, and hence, improves overall sensor performance. In this structure, an antiblooming potential barrier is provided that is smaller (in volts) than the barriers that separate the pixels from one another so that excess charge will flow preferentially into the LOD as opposed to the adjacent pixels.

Abstract: The new CCD output region provides a method of reducing the width of a wide CCD at its output to maintain a high sensitivity output node without sacrificing charge-transfer efficiency. A barrier region is shaped so the "channel width" of the CCD increases towards the input edge of the output gate. The barrier region, therefore, decreases in width towards the output end of the final CCD phase of a multi-phase device. Also, the channel width under the output gate decreases towards its output end in the direction of charge transfer towards the floating diffusion, or detection node. Since the "shaped" portion of the barrier region under the last CCD phase can be formed by the same process steps as the regular-shaped barrier regions, it is possible to form this structure without the requirement for additional masking and implant steps. The advantages of this structure over the prior art are improved charge-transfer characteristics without requiring additional process steps.

Abstract: The new CCD output region provides a method of reducing the width of a wide CCD at its output to maintain a high sensitivity output node without sacrificing charge-transfer efficiency. A barrier region is shaped so the "channel width" of the CCD increases towards the input edge of the output gate. The barrier region, therefore, decreases in width towards the output end of the final CCD phase of a multi-phase device. Also, the channel width under the output gate decreases towards its output end in the direction of charge transfer towards the floating diffusion, or detection node. Since the "shaped" portion of the barrier region under the last CCD phase can be formed by the same process steps as the regular-shaped barrier regions, it is possible to form this structure without the requirement for additional masking and implant steps. The advantages of this structure over the prior art are improved charge-transfer characteristics without requiring additional process steps.

Abstract: An electronic imaging system is provided that records both motion and still video images. In a motion mode of operation, the electronic imaging system records NTSC resolution images at a standard thirty frame per second rate. In a still mode of operation, the electronic imaging system records megapixel resolution still images at a much lower frame rate. The electronic imaging system utilizes an electronic image sensor that incorporates column selective "charge clearing" structures and column selective "charge parking" structures. The charge clearing structures are used to selectively discard the signal charge from certain color pixels. The charge parking structures are used to sum the charge from multiple vertical pixels. The architecture of the electronic image sensor also allows different image aspect ratios to be provided for the motion and still modes described above.

Abstract: Solid-state image sensors, in general, comprise a photodetector for detecting radiation from the image and converting the radiation to charge carriers, and transfer means for carrying the charge carriers to an output circuit. One type of solid-state image sensor uses a CCD as both the photodetector and the transfer means. The solid-state image sensor generally includes a plurality of the CCD's arranged in spaced parallel relation to form an array. The image sensor of this disclosure utilizes only one antiblooming lateral overflow barrier. The excess signal charge of phase 1 flows into the preceding phase 2 and is saved. This eliminates the overflow barrier of phase 1 so that blooming protection is via the overflow barrier of the preceding phase 2. This results in an image sensor with blooming protection and increased charge capacity.

Abstract: An image sensor having improved antiblooming characteristics includes a plurality of photodetectors in a substrate at a surface thereof and arranged in an array of columns and rows. A CCD shift register extends along each column of the photodetectors. A separate overflow drain is adjacent each photodetector and an overflow barrier extends between each photodetector and its adjacent drain. Each photodetector has an active region of one conductivity type which is divided into first and second portions. The first portion of the active region has a higher concentration of the impurities of the one conductivity type than the second portion so as to have a lower potential during operation thereof. Thus, the charge carriers generated in the first portion will flow into the second portion where they are stored. This reduces the capacitance of the photodetector to increase it antiblooming characteristics while maintaining the sensitivity of the photodetector.

Abstract: The present invention is directed to a method of making a true two-phase CCD using a single layer (level) of the conductive material for the gate electrodes to provide a planar structure. The method includes using L-shaped masking layers having a submicron length of a bottom portion between two masking layers of silicon dioxide on and spaced along a surface of a conductive layer. The conductive layer is over and insulated from a surface of a body of a semiconductor material having a channel region therein. The L-shaped masking layers are removed to expose a spaced narrow portions of the conductive layer. The conductive layer is then etched completely therethrough at each exposed portion to divide the conductive layer into gate electrodes which are spaced apart by submicron width gaps.

Abstract: A method of making a two-phase charge coupled device (CCD) includes forming a layer of a conductive material over and insulated from the surface of a body of a semiconductor material of one conductivity type having a channel region of the opposite conductivity type in the body and extending to the surface. Sections of a first masking layer are formed on the conductive material layer spaced along the channel region. A conductivity modifying dopant is implanted into the channel region through the spaces between the sections of the first masking layer. A layer of a second masking layer is formed over the sections of the first masking layer and on the surface of the conductive material layer in the spaces between the sections of the first masking layer. A layer of indium-tin oxide (ITO) is formed over the portions of the second masking layer which extend across the ends of the sections of the first masking layer, and a layer of carbon is formed on the second masking layer between the ITO layers.

Abstract: In a solid state image sensor, such as a CCD image sensor having lateral antiblooming protection, the level of which is controlled by an overflow gate voltage forming a barrier, the storage of electrons in the photodiode junction region of the sensor is eliminated by removing the barrier and allowing the charge to flow from the sensor's photodiode junctions into the overflow region. The charge flow is then detected as a function of the instantaneous light impinging on the photodiodes. The physical connections of the overflow gates are selected to form zones. Since the charge flow now represent the instantaneous light intensity, higher frequency components are detected than that limited by the sensor sampling rate. An amplifier is connected to sense the charge flow from each zone. With the range of light intensity being large the amplifier is provided with a logarithmic feed back element. This element provides compression of a signal representing the sensed charge flow.

Abstract: A frame transfer image sensor having a lateral overflow drain and a structure for controlling the charge transfer to the drain during charge collection to improve exposure latitude.

Abstract: An image sensor including CCDs, a charge coupled device (CCD) or shift register. Each CCD structure is formed of a set of electrodes wherein at least one electrode of each set is formed of a connected layer of opaque conducting material.

Abstract: An interline transfer type area image sensor which operates in a non-interlaced mode and has an array of columns and rows of photoreceptor in which charge from each pixel is transferred into a stage of a vertical two-phase CCD shift register formed by adjacent electrodes of the CCD. Each electrode of a stage has a separate voltage clock. An ion implanted vertical transfer barrier region is formed under an edge of each electrode.

Abstract: The present invention is directed to an image sensor which comprises a body of a semiconductor material having therein a plurality of photodetectors arranged in a line and a CCD shift register extending along the line of photodetectors adjacent to but spaced from an edge of the photodetectors. The CCD shift register includes a channel region and a plurality of first and second gate electrodes extending over and insulated from the channel region. One of each of the first and second gate electrodes extends across a portion of the edge of each photodetector. Each of the first electrodes has an arm extending along the entire edge of its respective photodetector between the photodetector and the second gate electrode. A separate transfer region is in the body between the edge of each photodetector and its respective first electrode and extends along the entire edge of the photodetector. A transfer gate is over and insulated from the transfer regions.

Abstract: A high-gain, low-noise transistor amplifier comprises an input, an output, and first and second field effect transistors each having a gate, a drain, and a source and being formed in a common semiconductor substrate. The second transistor is a depletion mode transistor if it is of the same conductivity type as the first but is an enhancement mode transistor if it is of opposite conductivity type with respect to the first. In an amplifier configuration, the input is coupled to the gate of the first transistor, the source of the first transistor is coupled to the gate of the second transistor, the source of the second transistor is coupled to the output, and there is a direct-coupled feedback path from the source of the second transistor to the drain of the first transistor. At least the first transistor is formed in an isolated well of conductivity opposite to that of the substrate in the semiconductor substrate and its source is coupled directly to that well.

Abstract: An output circuit for sequentially receiving and converting charge collected in the photoelements of an image sensor and converting such charge into an output voltage. The output circuit includes a buried-channel LDD transistor having gate, source and drain electrodes. The source electrode provides a floating diffusion. When the transistor is turned off, a potential well is provided in the floating diffusion which collects charge. An output source-follower amplifier also employing buried-channel LDD transistors is connected to the floating diffusion and produces the output voltage.

Abstract: A solid-state image sensor includes a substrate of a semiconductor material of one conductivity type having a surface. A plurality of spaced, parallel CCDs are in the substrate at the surface. Each CCD includes a channel region of the opposite conductivity type in the substrate and a plurality of conductive gates extending across and insulated from the channel region. The conductive gates extend laterally across the channel regions of all of the CCDs and divide the channel regions into a plurality of phases and pixels. A drain region of the opposite conductivity type is in the substrate at the surface and extends along the channel region of at least one of the CCDs. A separate overflow channel region of the opposite conductivity type is in the substrate at said surface and extends from each of the CCD channel region phases to the adjacent drain region.