Abstract: A method for fabricating corner implants in the shallow trench isolation regions of an image sensor includes the steps of forming a photoresist layer on a first hard mask layer overlying an etch-stop layer on a semiconductor substrate. The photoresist mask is patterned to create an opening and the portion of the first hard mask layer exposed in the opening is etched down to the etch-stop layer. A first dopant is implanted into the semiconductor substrate through the exposed etch-stop layer. The photoresist mask is removed and a second hard mask layer is formed on the remaining structure and etched to create sidewall spacers along the side edges of the first hard mask layer. The etch stop layer and the semiconductor substrate positioned between the sidewall spacers are etched to create a trench and a second dopant implanted into the side and bottom walls of the trench.

Abstract: An image sensor includes a substrate containing photosensitive areas; an insulator spanning the substrate; and a first and second layer of a multi-layer metalization structure wherein the first layer forms the light shield regions over portions of the photosensitive area as well as forming circuit interconnections and barrier regions to prevent spiking into the substrate or gates at contacts in the non-imaging area, and the second layer spanning the interconnections and barrier regions of the first layer only over the non-imaging area.

Abstract: An image sensor includes a substrate having photosensitive areas; an insulator spanning the substrate; and a first and second layer of a multi-layer metallization structure, wherein the first layer forms light shield regions over selected portions of the photosensitive area as well forming circuit interconnections and barrier regions to prevent spiking into the substrate or gates at contacts in the non-imaging area; and the second layer spanning the interconnections and barrier regions of the first layer only over the non-imaging areas and the second layer overlays edges of the first layer.

Abstract: An image sensor includes a substrate containing photosensitive areas; an insulator spanning the substrate; and a first and second layer of a multi-layer metalization structure wherein the first layer forms the light shield regions over portions of the photosensitive area as well as forming circuit interconnections and barrier regions to prevent spiking into the substrate or gates at contacts in the non-imaging area, and the second layer spanning the interconnections and barrier regions of the first layer only over the non-imaging area.

Abstract: An optically operated test structure for testing the charge transfer efficiency (CTE) of a charge coupled device (CCD) solid-state image sensor. A solid-state image sensor includes a substrate of a semiconductor material of one conductivity type having a surface. A plurality of spaced, parallel CCDs are in the substrate at the surface. Each CCD includes a channel region and a plurality of conductive gates extending across and insulated from the channel region. The conductive gates extend laterally across the channel regions of all of the CCDs and divide the channel regions into a plurality of phases and pixels. A drain region of the opposite conductivity type is in the substrate at the surface and extends along the channel region of at least one of the CCDs. A simply connected (rectangular) region of the plurality of spaced, parallel CCDs is photoactive. The CCDs outside this photoactive region are typically covered with metal or some other optically opaque material.

Abstract: A method for creating a lateral overflow drain, anti-blooming structure in a charge-coupled device, the method includes the steps of providing a substrate of a first conductivity type; providing a layer of silicon dioxide on the substrate; providing a layer of silicon nitride on the silicon dioxide layer; providing a first masking layer on the silicon nitride layer and having an opening in the first masking layer of a dimension which substantially equals a dimension of a subsequently implanted channel stop of the first conductivity type; etching away the exposed silicon nitride within the opening in the first masking layer; implanting ions of the first conductivity type through the first masking layer and into the substrate for creating the channel stop and removing the first masking layer; growing the silicon dioxide layer so that the channel stop is spanned by a thickest field silicon dioxide layer in the etched away portion; patterning a second masking layer having an opening adjacent the channel stop with

Abstract: A CMOS image sensor comprises a substrate of a first conductivity type, a photodetector for capturing incident light and converting it to a charge; a transfer gate for passing the charge from the photodetector; and a region of the first conductivity type of enhanced conductivity in the substrate which extends substantially along an entire length and width of the transfer gate.

Abstract: A structure for a fast-dump gate for charge coupled devices that does not require a separate contact to a drain region instead using the existing drain of a lateral overflow drain (LOD) typically used for antiblooming purposes. LOD structures are typically used on full-frame CCD image sensors. By using the LOD as the drain for a fast-dump gate, a separate opening in the gate electrode for the drain contact is avoided, thereby making the structure more compact. Gate control is provided by etching a hole in the CCD gate electrode over the overflow channel region of the LOD structure, and overlaying this with one of the subsequent gate electrode layers. This subsequent gate electrode is then used to control the fast-dump operation. Timing is shown for a two-phase CCD being operated with accumulation-mode clocking. Other types of CCDs and clocking schemes may be used.

Abstract: The present invention is a structure for a fast-dump gate (FDG) and a fast-dump drain (FDD) for a charge coupled device. It is envisioned that the charge coupled device be a horizontal readout register of a solid-state image sensor. This structure uses a third layer of polysilicon (or other suitable gate material) to form the fast-dump gate which is in addition to the other two layers of gate material used to form the gates in the horizontal readout register. This allows the channel region under the fast-dump gate (FDG) to form without the use of highly-doped channel stop regions thereby eliminating any potential wells or barriers that may result in transfer inefficiency often time found with other structures.

Abstract: An image sensor having an anti-blooming structure, where the image sensor comprises a substrate of a first conductivity type; a dielectric having a first thin portion and a second thick portion; a buried channel of the second conductivity type within the substrate substantially spanning the first thin portion; and a lateral overflow drain region of the second conductivity type disposed substantially in its entirety spanning a portion of the second thick portion for collecting excess photogenerated charges for preventing blooming.

Abstract: A method of creating a lateral overflow drain, anti-blooming structure in a charge coupled device, the method includes steps for self-aligning a peripheral edge of the lateral overflow drain to an edge of the thick field oxide, whereby the overflow drain is substantially covered by the field oxide.

Abstract: The present invention is a structure for a fast-dump gate (FDG) and a fast-dump drain (FDD) for a charge coupled device. It is envisioned that the charge coupled device be a horizontal readout register of a solid-state image sensor. This structure uses a third layer of polysilicon (or other suitable gate material) to form the fast-dump gate which is in addition to the other two layers of gate material used to form the gates in the horizontal readout register. This allows the channel region under the fast-dump gate (FDG) to form without the use of highly-doped channel stop regions thereby eliminating any potential wells or barriers that may result in transfer inefficiency often time found with other structures.

Abstract: An image sensor having an anti-blooming structure, where the image sensor comprises a substrate of a first conductivity type; a dielectric having a first thin portion and a second thick portion; a buried channel of the second conductivity type within the substrate substantially spanning the first thin portion; and a lateral overflow drain region of the second conductivity type disposed substantially in its entirety spanning a portion of the second thick portion for collecting excess photogenerated charges for preventing blooming.

Abstract: A method for creating a lateral overflow drain, anti-blooming structure in a charge coupled device, the method includes the steps of providing a substrate of a first conductivity type for the charge coupled device; providing a layer of oxide abutting the substrate; providing a layer of nitride abutting the oxide; providing a hard mask abutting the nitride with an etched away portion having a dimension which substantially equals a combined dimension of heavily doped first and second conductivity type subsequently implanted regions in the substrate; placing photoresist in a portion of the etched away portion which remaining etched away portion includes a dimension substantially equal to the first conductivity type subsequently implanted region in the substrate; implanting ions of the first conductivity type through the remaining etched away portion and into the substrate for creating a channel stop; removing the photoresist and placing a second photoresist layer in a portion of the etched away portion wherein a

Abstract: The present invention is a structure for a fast-dump gate (FDG) and a fast-dump drain (FDD) for a charge coupled device. It is envisioned that the charge coupled device be a horizontal readout register of a solid-state image sensor. This structure uses a third layer of polysilicon (or other suitable gate material) to form the fast-dump gate which is in addition to the other two layers of gate material used to form the gates in the horizontal readout register. This allows the channel region under the fast-dump gate (FDG) to form without the use of highly-doped channel stop regions thereby eliminating any potential wells or barriers that may result in transfer inefficiency often time found with other structures.

Abstract: A charge-coupled device (CCD) image sensor that preserves defect gettering characteristics having a vertical overflow drain (VOD) for blooming protection is provided in a structure that provides low voltage electronic shuttering. This structure reduces the electronic shutter voltage to ease the demands on off-chip support circuitry required to operate the CCD image sensor. The invention provides an improved pixel structure to reduce this voltage. Prior art difficulties are avoided by providing uniform, n-type layers of varying doping levels underneath the entire area of the CCD device. Combined with a lightly doped n-type substrate these layers provide low voltage electronic shutter operation.

Abstract: An optically operated test structure for testing the charge transfer efficiency (CTE) of a charge coupled device (CCD) solid-state image sensor. A solid-state image sensor includes a substrate of a semiconductor material of one conductivity type having a surface. A plurality of spaced, parallel CCDs are in the substrate at the surface. Each CCD includes a channel region and a plurality of conductive gates extending across and insulated from the channel region. The conductive gates extend laterally across the channel regions of all of the CCDs and divide the channel regions into a plurality of phases and pixels. A drain region of the opposite conductivity type is in the substrate at the surface and extends along the channel region of at least one of the CCDs.

Abstract: A method and apparatus of making high energy implanted photodiode that is self aligned with the transfer gate, the high energy implant is defined by providing a substrate, or well, of a first conductivity type, defining a charge coupled device within the substrate, or well, such that gate electrode layers are allowed to exist over areas to contain photodiodes during construction of the charge coupled device, patterning a masking layer to block high energy implants such that openings in the masking layer are formed over the areas of the photodiodes, anisotropically etching down through the gate electrode over the photodiodes to the gate dielectric material, implanting photodiodes with high-energy ions of a second conductivity type opposite the first conductivity type and creating a pinned photodiode by employing a shallow implant of the first conductivity type. The apparatus made by this method yields a photodiode employing high energy ions to form the P/N junction that is self aligned with the transfer gate.

Abstract: The optimization of two technologies (CMOS and CCD) wherein a pinned photodiode is integrated into the image sensing element of an active pixel sensor. Pinned photodiodes are fabricated with CCD process steps into the active pixel architecture. Charge integrated within the active pixel pinned photodiode is transferred into the charge sensing node by a transfer gate. The floating diffusion is coupled CMOS circuitry that can provide the addressing capabilities of individual pixels. Alternatively, a buried channel photocapacitor can be used in place of the pinned photodiode.

Abstract: A self aligned, lateral-overflow drain antiblooming structure that is insensitive to drain bias voltages and therefore has improved insensitivity to process variations. The length of the antiblooming barrier regions are easily adjusted and determined by photolithography. The self aligned, lateral-overflow drain (LOD) antiblooming structure results in a design that saves space, and hence, improves overall sensor performance. In this structure, an antiblooming potential barrier is provided that is smaller (in volts) than the barriers that separate the pixels from one another so that excess charge will flow preferentially into the LOD as opposed to the adjacent pixels.