Abstract: An apparatus includes a memory and a controller. The memory may be configured to store data. The controller may be configured to process a plurality of read/write operations to/from the memory, receive a codeword from the memory, generate a plurality of syndromes of the codeword at a plurality of possible code rates, generate a plurality of count values by counting a number of unsatisfied parity checks in each of the plurality of syndromes, generate a plurality of normalized values by dividing the plurality of count values by a plurality of lengths of the plurality of possible code rates respectively, and determine a bit error rate value of the memory based on a lowest value among the plurality of normalized values.

Abstract: Systems and method relating generally to solid state memory, and more particularly to systems and methods for recycling data in a solid state memory. The systems and methods include receiving a data set maintained in a memory device, applying at least one iteration of a data decoding algorithm to the data set by a data decoder circuit to yield a decoded output, counting the number of iterations of the data decoding algorithm applied to the data set to yield an iteration count, and recycling the data set to the memory device. The recycling is triggered based at least in part on the iteration count.

Abstract: An apparatus comprising a memory and a controller. The memory is configured to process a plurality of read/write operations. The memory comprises a plurality of memory modules. Each memory module has a size less than a total size of the memory. The controller is configured to (i) classify data from multiple blocks of the memory as hot-read data or non hot-read data, (ii) aggregate the hot-read data to dedicated blocks, and (iii) select a type of error correcting code to protect the hot-read data in the dedicated blocks. The aggregation reduces an impact on endurance of the memory.

Abstract: Systems and methods relating generally to data processing, and more particularly to systems and methods for characterizing a solid state memory. In one embodiment, the systems and methods may include programming a first cell of a solid state memory device to a negative voltage, programming a second cell of the solid state memory device to a positive voltage, wherein the second cell is adjacent to the first cell, calculating a voltage shift on the negative voltage programmed to the first cell, characterizing a shifted voltage level on the first cell as an interim voltage, and subtracting the voltage shift from the interim voltage to yield an actual voltage on the first cell.

Abstract: Methods and apparatus are provided for processing a data value in a read channel of a memory device. The data value provided to a general purpose processor for processing. The data value is not decoded data and may comprise one or more of a raw data value and an intermediate data value. The data value can be provided to the general purpose processor, for example, upon a detection of one or more predefined trigger conditions. A data value can be obtained from a memory device and then be redirected to a general purpose processor. The data value is not decoded data. The redirection can be conditionally performed if one or more predefined bypass conditions exist. The general purpose processor is optionally time-shared with one or more additional applications.

Abstract: Systems and method relating generally to solid state memory, and more particularly to systems and methods for recycling data in a solid state memory. The systems and methods include receiving a data set maintained in a memory device, applying at least one iteration of a data decoding algorithm to the data set by a data decoder circuit to yield a decoded output, counting the number of iterations of the data decoding algorithm applied to the data set to yield an iteration count, and recycling the data set to the memory device. The recycling is triggered based at least in part on the iteration count.

Abstract: A syndrome weight of failed decoding attempts is used to select parameters for future read retry operations. The following exemplary steps are performed until a decoding success or a predefined limited number of readings is reached: (i) reading a codeword using different read threshold voltages; (ii) mapping the readings to a corresponding likelihood value using a likelihood value assignment; and (iii) recording a syndrome weight for failed decoding attempts of the readings using the different read threshold voltages.

Abstract: An apparatus includes a memory and a controller. The memory includes a plurality of memory devices. The controller may be coupled to the memory and configured to process a plurality of read/write operations to/from the memory, store data in the plurality of memory devices using units of super-blocks, and generate a number of unique weight statistics in a single read operation by reading a number of dies within a super-block with dissimilar read reference voltages. Each super-block generally includes a block from a die of each of the plurality of memory devices. The controller may be further configured to split the number of dies in each super-block into two sets and collect page weights for upper pages from one of the two sets and page weights for lower pages from the other of the two sets.

Abstract: Systems and methods relating generally to data processing, and more particularly to systems and methods for characterizing a solid state memory. In one embodiment, the systems and methods may include programming a first cell of a solid state memory device to a negative voltage, programming a second cell of the solid state memory device to a positive voltage, wherein the second cell is adjacent to the first cell, calculating a voltage shift on the negative voltage programmed to the first cell, characterizing a shifted voltage level on the first cell as an interim voltage, and subtracting the voltage shift from the interim voltage to yield an actual voltage on the first cell.

Abstract: Systems and methods for internal copy-back with read-verify are described. In one embodiment, a storage device includes a controller to select a first single level cell (SLC) page of a plurality of SLC pages on the storage device to transfer to a triple level cell (TLC) page. The controller, in conjunction with an error correcting code (ECC) decoder, read-verifies the first SLC page. Read-verifying the first SLC page includes reading the first SLC page to an internal page buffer, decoding the first SLC page read into the internal page buffer, determining a number of errors contained in the first SLC page based at least in part on the decoding, and verifying whether the number of errors contained in the first SLC page satisfies an error threshold. The controller transfers the first SLC page to the TLC page according to a result of read-verifying the first SLC page.

Abstract: Channel information and channel conditions determined by an Offline Tracking process are used to determine whether or not an adjustment to the read reference voltage can be avoided altogether without detrimentally affecting performance, or, alternatively, to determine a precision with which a read reference voltage adjustment should be made. If it is determined based on the channel conditions that a read reference voltage adjustment can be avoided altogether, read performance is improved by reducing the probability that a read reference voltage adjustment needs to be made during normal read operations. If it is determined based on the channel conditions that a read reference voltage adjustment needs to be made with a particular precision, the read reference voltage is so adjusted. This latter approach is advantageous in that relatively fewer adjustments will be made during normal read operations.

Abstract: An apparatus includes a memory and a controller. The memory may be configured to store data. The controller may be configured to process a plurality of input/output requests to a plurality of blocks of the memory that are not marked as bad on a block list, perform a code rate test that programs the plurality of blocks of the memory at three or more code rates of an error correction code scheme, and mark any of the plurality of blocks identified as bad during the code rate test on the block list.

Abstract: An apparatus includes a memory and a controller. The memory may be configured to store data. The memory generally comprises a plurality of memory units each having a size less than a total size of the memory. The controller may be configured to generate a set of converted log likelihood ratios by scaling a set of original log likelihood ratios using a selected scalar value, wherein the controller determines the selected scalar value by generating a plurality of sets of scaled log likelihood ratios by scaling the set of original log likelihood ratios with a plurality of corresponding scalar values, calculating a plurality of respective correlation coefficients each measuring a similarity of a respective set of scaled log likelihood ratios to the set of original log likelihood ratios, and selecting the scalar value corresponding to the set of scaled log likelihood ratios whose respective correlation coefficient is highest as the selected scalar value.

Abstract: An apparatus includes a plurality of memory devices and a controller. The controller is coupled to the plurality of memory devices and configured to store data in the plurality of memory devices using units of super-blocks. Each super-block comprises a block from each of the plurality of memory devices and the controller balances time efficiency and robustness during collection of statistics from soft reads of each super-block.

Abstract: Methods and apparatus are provided for read retry operations that estimate written data based on syndrome weights. One method comprises reading a codeword from a memory multiple times using multiple read reference voltages; obtaining a syndrome weight for each of the readings of the codeword; identifying a given reading of the codeword having a substantially minimum syndrome weight; and estimating a written value of the codeword based on the given reading. Two cell voltage probability distributions of cell voltages are optionally calculated for each possible cell state of the memory, based on the estimated written value and plurality of readings of the codeword. The cell voltage probability distributions are used to (i) dynamically select log likelihood ratio values for a failing page. (ii) determine a read reference voltage that gives a desired log likelihood ratio value, or (iii) dynamically select log likelihood ratio values for the page populations associated with the distributions.

Abstract: Methods and apparatus are provided for adaptive read threshold voltage tracking with separate characterization on each side of a voltage distribution about a distribution mean. A read threshold voltage for a memory is adjusted by determining statistical characteristics of two adjacent memory levels based at least in part on a type of statistical distribution of the memory levels and a distribution of data values read from cells using a plurality of read threshold voltages, wherein the statistical characteristics of the two adjacent memory levels are characterized independently on two sides about at least one mean of the statistical distribution; computing an adjusted read threshold voltage associated with the two adjacent memory levels by using the statistical characteristics of the two adjacent memory levels; and updating the read threshold voltage based on the adjusted read threshold voltage. The adjustment is optionally performed responsive to one or more read errors.

Abstract: An apparatus includes an interface and a control circuit. The interface may be configured to process read/write operations to/from a memory. The control circuit may be configured to create dependencies between a current bit in a sequence of data bits and neighboring bits in the sequence of data bits to generate mapped bits in response to a condition in a region of the memory being true, write the mapped bits among at least two memory cells in the region of the memory with at least two of the mapped bits stored in each of the memory cells, where the dependencies mitigate a hard error due to one of the at least two cells being stuck in a fixed state, and write the sequence of data bits in the region of the memory in response to the condition in the region of the memory being false.

Abstract: Methods and apparatus are provided for adaptive read threshold voltage tracking with gap estimation between default read threshold voltages. A read threshold voltage for a memory is adjusted by estimating a gap between two adjacent default read threshold voltages; determining statistical characteristics of two adjacent memory levels based at least in part on a type of statistical distribution of the memory levels, a distribution of data values read from one or more cells using a plurality of read threshold voltages and the gap; computing an adjusted read threshold voltage associated with the two adjacent memory levels by using the statistical characteristics of the two adjacent memory levels; and updating the read threshold voltage with the adjusted read threshold voltage. The adjustment is optionally performed responsive to one or more read errors.

Abstract: A read threshold voltage for a memory is adjusted based on a bit error rate based on decoded data for a plurality of read threshold voltages. The read threshold voltage can be adjusted by reading the memory at a current read threshold voltage to obtain a read value; applying a hard decision decoder to the read value; determining if the hard decision decoder converges for the read value to a converged word; storing bits corresponding to the converged word as reference bits and, if the hard decision decoder converges, (i) computing a bit error rate for the current read threshold voltage based on the reference bits; (ii) adjusting the current read reference voltage to a new read threshold voltage; and (iii) reading the memory at the new read threshold voltage to obtain a new read value, until a threshold is satisfied; and once the threshold is satisfied, selecting the read threshold voltage based on the bit error rates.

Abstract: Read retry operations in a memory employ likelihood value assignments that change sign at different read voltages for a plurality of read retry operations. A method for multiple read retries of a memory comprises reading a codeword using a first read voltage to obtain a first read value; mapping the first read value to first likelihood values based on a first likelihood value assignment that changes sign substantially at the first read voltage; reading the codeword using a second read voltage to obtain a second read value, wherein the second read voltage is shifted from the first read voltage to compensate for an expected change in analog voltages; and mapping the second read value to second likelihood values based on a second likelihood value assignment, wherein the second likelihood value assignment changes sign substantially at the second read voltage. Read data is optionally generated using iterative decoding of the codeword based on the first likelihood values and/or the second likelihood values.