Abstract: Disclosed is a device comprising a circuit having an active side and a non-active side, a package enclosing the active side of the circuit and not enclosing a portion of the non-active side of the circuit, and a lead having a first end connected to the active side of the circuit via a lead-over-chip connection, and having a second end extending from the package. Also disclosed is a device comprising a circuit and a lead formed from a flexible conductor, with the lead having a first end connected to the circuit.

Abstract: A device comprising a circuit, a lead having a first end connected to the circuit and having a second end, and a deformable structure connected to the second end of the lead. The invention may be embodied on a circuit board, so that the circuit board includes a substrate and a deformable structure connected to said substrate.

Abstract: An illustrative embodiment of the present invention includes a non-volatile, reprogrammable circuit switch. The circuit switch includes a metal oxide semiconductor field effect transistor (MOSFET) in a substrate. The MOSFET has a source region, a drain region, a channel region between the source and drain regions, and a gate separated from the channel region by a gate oxide. According to the teachings of the present invention, the MOSFET is a programmed MOSFET having a charge trapped in the gate oxide adjacent to the source region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2).

Abstract: A semiconductor device assembly includes a first semiconductor die, such as a logic device, with bond pads arranged in an array on an active surface thereof, and at least one second semiconductor die, such as a memory device or an ancillary or parallel logic device, with bond pads on an active surface thereof with active surfaces thereof facing each other. Corresponding bond pads of the first and at least one second semiconductor dice are connected to each other by way of conductive structures disposed therebetween. The package includes the assembly and a carrier, such as a carrier substrate or leads. The first semiconductor die is oriented over the carrier such that bond pads thereof that are exposed beyond the periphery of each second semiconductor die face the carrier and are electrically connected to corresponding contacts thereof.

Abstract: A memory device comprising a compression and decompression engine and a error detection and correction engine connected between a cache memory and a main memory in the same semiconductor chip.

Abstract: A semiconductor wafer having dice that include circuitry that is placed into a mode when the circuitry receives an alternating signal having certain characteristics. The alternating signal may be supplied from a system controller through a probe, probe pad, and conductive path on the wafer. In a preferred embodiment, the conductive path simultaneously carries a VCC power signal and the alternating signal to the circuitry. However, the alternating signal may be carried on a conductive path different from the one carrying the VCC signal. A great deal of information may be conveyed through the alternating signal, making other signals unnecessary in controlling, testing, stressing, and repairing dice on the wafer. For example, clocking information may be conveyed through the alternating signal. The circuitry may be placed in different modes in response to different characteristics of the alternating signal. The alternating signal and a VCC power signal are received through a single contact on each die.

Abstract: A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.

Abstract: Imaging arrays typically include thousands or millions of photodetectors that convert sensed light into corresponding electric signals, which are ultimately converted into digital image signals for recording or viewing. One problem with conventional imaging arrays concerns faulty photodetectors, which produce erroneous image signals that ultimately degrade the quality of resulting images. Accordingly, the present inventors devised new imaging arrays including redundant photodetectors to compensate for faulty ones. One exemplary embodiment includes photodetectors that are substantially smaller than conventional photodetectors and that are arranged into two or more groups, with the photodetectors in each group coupled to produce a single group image signal. If the group image signal for a group falls below some threshold level indicative of a defective or malfunctioning photodetector, the group image signal is amplified to compensate for the loss.

Abstract: Imaging arrays typically include thousands or millions of photodetectors that convert sensed light into corresponding electric signals, which are ultimately converted into digital image signals for recording or viewing. One problem with conventional imaging arrays concerns faulty photodetectors, which produce erroneous image signals that ultimately degrade the quality of resulting images. Accordingly, the present inventors devised new imaging arrays including redundant photodetectors to compensate for faulty ones. One exemplary embodiment includes photodetectors that are substantially smaller than conventional photodetectors and that are arranged into two or more groups, with the photodetectors in each group coupled to produce a single group image signal. If the group image signal for a group falls below some threshold level indicative of a defective or malfunctioning photodetector, the group image signal is amplified to compensate for the loss.

Abstract: A semiconductor wafer having dice that include circuitry that is placed into a mode when the circuitry receives an alternating signal having certain characteristics. The alternating signal may be supplied from a system controller through a probe, probe pad, and conductive path on the wafer.

Abstract: The present invention includes a programmable logic array having a first logic plane that receives a number of input signals. The first logic plane has a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logical outputs. A number of non-volatile memory cells arranged in rows and columns of a second logic plane receive the outputs of the first logic plane and are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function. Each non-volatile memory cell includes a MOSFET. Each non-volatile memory cell includes a stacked capacitor formed according to a DRAM process. Each nonvolatile memory cell includes an electrical contact that couples the stacked capacitor to a gate of the MOSFET. The present invention also includes methods for producing the Ics and arrays.

Abstract: An illustrative embodiment of the present invention includes a non-volatile, reprogrammable circuit switch. The circuit switch includes a metal oxide semiconductor field effect transistor (MOSFET) in a substrate. The MOSFET has a source region, a drain region, a channel region between the source and drain regions, and a gate separated from the channel region by a gate oxide. According to the teachings of the present invention, the MOSFET is a programmed MOSFET having a charge trapped in the gate oxide adjacent to the source region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2).

Abstract: A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.

Abstract: Imaging arrays are electronic devices that sense light and output electrical signals representative of the sensed light. An imaging array comprises thousands or millions of photodetectors that convert sensed light into corresponding electric signals, which are ultimately converted into digital image signals for recording or viewing. One problem with conventional imaging arrays concerns defective or malfunctioning photodetectors. Defective photodetectors typically result in erroneous image signals that ultimately degrade the quality of resulting images. Accordingly, the present inventors devised new imaging arrays including redundant photodetectors to compensate for defective photodetectors. One exemplary embodiment includes one or more photodetectors that are substantially smaller than conventional photodetectors, for example about 10 or 25 square microns.

Abstract: The present invention includes a programmable logic array having a first logic plane that receives a number of input signals. The first logic plane has a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logical outputs. A number of non-volatile memory cells arranged in rows and columns of a second logic plane receive the outputs of the first logic plane and are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function. Each non-volatile memory cell includes a MOSFET. Each non-volatile memory cell includes a stacked capacitor formed according to a DRAM process. Each non-volatile memory cell includes an electrical contact that couples the stacked capacitor to a gate of the MOSFET. The present invention also includes methods for producing the Ics and arrays.

Abstract: An improved integrated circuit package for providing built-in heating or cooling to a semiconductor chip is provided. The improved integrated circuit package provides increased operational bandwidth between different circuit devices, e.g. logic and memory chips. The improved integrated circuit package does not require changes in current CMOS processing techniques. The structure includes the use of a silicon interposer. The silicon interposer can consist of recycled rejected wafers from the front-end semiconductor processing. Micro-machined vias are formed through the silicon interposer. The micro-machined vias include electrical contacts which couple various integrated circuit devices located on the opposing surfaces of the silicon interposer. The packaging includes a Peltier element.

Abstract: Structures and methods for PLA capability on a DRAM chip according to a DRAM optimized process flow are provided by the present invention. These structures and methods include using MOSFET devices as re-programmable elements in memory address decode circuits in a DRAM integrated circuit. The structures and methods use the existing process sequence for MOSFET's in DRAM technology. In particular, an illustrative embodiment of the present invention includes a non-volatile, reprogrammable circuit switch. The circuit switch includes a metal oxide semiconductor field effect transistor (MOSFET) in a substrate. The MOSFET has a source region, a drain region, a channel region between the source and drain regions, and a gate separated from the channel region by a gate oxide.

Abstract: A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.

Abstract: A semiconductor wafer having dice that include circuitry that is placed into a mode when the circuitry receives an alternating signal having certain characteristics. The alternating signal may be supplied from a system controller through a probe, probe pad, and conductive path on the wafer. In a preferred embodiment, the conductive path simultaneously carries a VCC power signal and the alternating signal to the circuitry. However, the alternating signal may be carried on a conductive path different from the one carrying the VCC signal. A great deal of information may be conveyed through the alternating signal, making other signals unnecessary in controlling, testing, stressing, and repairing dice on the wafer. For example, clocking information may be conveyed through the alternating signal. The circuitry may be placed in different modes in response to different characteristics of the alternating signal. The alternating signal and a VCC power signal are received through a single contact on each die.

Abstract: A dual FIFO architecture is described which allows internal read and write operations in a DRAM memory device to be decoupled from the read and write operations associated with the processor-memory bus. The application of separate read and write FIFO buffers interfaced with a plurality of memory banks on a DRAM memory device thus compensates for mismatches in communications speed that may exist between the rate at which data is provided to the memory banks from the processor-memory bus and likewise, the rate at which the memory banks can provide data to the processor-memory bus. Furthermore, the decoupling of internal memory operations with external reads and writes permits prioritization of read and write commands. Since the FIFOs serve directly as a data buffer to the memory banks, high speed computer operations is permitted because the microprocessor and the memory bus may operate at their own natural frequency without being restricted by the speed of the DRAM memory device.