Abstract: Improved methods and structures are provided for impedance-controlled low-loss lines in CMOS integrated circuits. The present invention offers a reduction in signal delay. Moreover, the present invention further provides a reduction in skew and crosstalk. Embodiments of the present invention also provide the fabrication of improved transmission lines for silicon-based integrated circuits using conventional CMOS fabrication techniques. One method of the present invention provides transmission lines in an integrated circuit. Another method includes forming transmission lines in a memory device. The present invention includes a transmission line circuit, a differential line circuit, a twisted pair circuit as well as systems incorporating these different circuits all formed according to the methods provided in this application.

Abstract: Structures and methods involving n-channel flash memories with an ultrathin tunnel oxide thickness, have been provided. Both the write and erase operations are performed by tunneling. According to the teachings of the present invention, the n-channel flash memory cell with thin tunnel oxides will operate on a dynamic basis. The stored data can be refreshed every few seconds as necessary. However, the write and erase operations will however now be orders of magnitude faster than traditional n-channel flash memory and the cell provides a large gain. The present invention further provides structures and methods for n-channel floating gate transistors which avoid n-channel threshold voltage shifts and achieve source side tunneling erase. The n-channel memory cell structure includes a floating gate separated from a channel region by an oxide layer of less than 50 Angstroms (Å).

Abstract: A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.

Abstract: The present invention includes an address decoder for a memory device. The address decoder includes a number of address lines and a number of output lines. The address lines, and the output lines form an array. A number of non-volatile memory cells are disposed at intersections of output lines and address lines. Each non-volatile memory cell includes a metal oxide semiconductor field effect transistor (MOSFET), a stacked capacitor formed according to a dynamic random access memory (DRAM) process, and an electrical contact that couples the stacked capacitor to a gate of the MOSFET. The non-volatile memory cells are selectively programmed such that the non-volatile memory cells implement a logic function that selects an output line responsive to an address provided to the address lines. Methods, integrated circuits, and electronic systems are similarly provided and included within the scope of the present invention.

Abstract: A semiconductor wafer having dice that include circuitry that is placed into a mode when the circuitry receives an alternating signal having certain characteristics. The alternating signal may be supplied from a system controller through a probe, probe pad, and conductive path on the wafer.

Abstract: A device comprising a circuit, a lead having a first end connected to the circuit and having a second end, and a deformable structure connected to the second end of the lead. The invention may be embodied on a circuit board, so that the circuit board includes a substrate and a deformable structure connected to said substrate. Also disclosed is a device comprising a circuit having an active side and a non-active side, a package enclosing the active side of the circuit and not enclosing a portion of the non-active side of the circuit, and a lead having a first end connected to the active side of the circuit via a lead-over-chip connection, and having a second end extending from the package. Also disclosed is a device comprising a circuit and a lead formed from a flexible conductor, with the lead having a first end connected to the circuit.

Abstract: A semiconductor wafer having dice that include circuitry that is placed into a mode when the circuitry receives an alternating signal having certain characteristics. The alternating signal may be supplied from a system controller through a probe, probe pad, and conductive path on the wafer.

Abstract: Structures and methods for novel DRAM technology compatible non volatile memory cells is provided. A non volatile memory cell structure is provided which includes a dynamic random access memory (DRAM) transistor. The non volatile memory cell includes a dynamic random access memory (DRAM) capacitor separated by an insulator layer from the DRAM transistor. An electrical via couples a first plate of the DRAM capacitor through the insulator layer to a gate of the DRAM transistor. The novel DRAM technology compatible non volatile memory cells can be fabricated on a DRAM chip with little or no modification of the DRAM optimized process flow. The novel DRAM technology compatible non volatile memory cells operate with lower programming voltages than that used by conventional non volatile memory cells, yet still hold sufficient charge to withstand the effects of parasitic capacitances and noise due to circuit operation.

Abstract: Improved methods and structures are provided for impedance-controlled low-loss lines in CMOS integrated circuits. The present invention offers a reduction in signal delay. Moreover, the present invention further provides a reduction in skew and crosstalk. Embodiments of the present invention also provide the fabrication of improved transmission lines for silicon-based integrated circuits using conventional CMOS fabrication techniques. Embodiments of a method for forming transmission lines in an integrated circuit include forming a first layer of electrically conductive material on a substrate. A first layer of insulating material is then formed on the first layer of electrically conductive material. The method also includes forming a pair of electrically conductive lines on the first layer of insulating material. Moreover, a transmission line is also formed on the first layer of insulating material.

Abstract: A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the shortcircuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.

Abstract: A memory device and method employing a scheme for reduced power consumption is disclosed. By dividing a memory array sector into memory sub arrays, the memory device can provide power to memory sub arrays that need to be powered up or, in the alternative, powered down. This reduces the power consumption and heat generation associated with high speed and high capacity memory devices.

Abstract: Thus, the ability to provide processor/PLA capability on a DRAM chip according to a DRAM optimized process flow has been shown by the present invention. This disclosure provides not only a technique for combining logic (implemented with PLA's) with stacked capacitor DRAM cells but also describes the alternative approach to improving system performance, namely “embedded logic in DRAMs”, not DRAMs embedded in logic.

Abstract: Structures and methods for PLA capability on a DRAM chip according to a DRAM optimized process flow are provided by the present invention. These structures and methods include using MOSFET devices as re-programmable elements in memory address decode circuits in a DRAM integrated circuit. The structures and methods use the existing process sequence for MOSFET's in DRAM technology.

Abstract: Structures and methods for novel DRAM technology compatible non volatile memory cells is provided. A non volatile memory cell structure is provided which includes a dynamic random access memory (DRAM) transistor. The non volatile memory cell includes a dynamic random access memory (DRAM) capacitor separated by an insulator layer from the DRAM transistor. An electrical via couples a first plate of the DRAM capacitor through the insulator layer to a gate of the DRAM transistor.

Abstract: Additional applications for DRAM technology compatible non-volatile memory cells are presented. The novel applications include the integration of DRAM technology compatible non-volatile memory cells which can be fabricated on a DRAM chip with little or no modification of the DRAM optimized process flow. The novel applications of DRAM technology compatible non-volatile memory cells operate with lower programming voltages than that used by conventional non-volatile memory cells, yet still hold sufficient charge to withstand the effects of parasitic capacitances and noise due to circuit operation. Hence, the requirements of low power densely packed integrated circuits is realized for smaller, portable microprocessor devices.

Abstract: An assembly includes a first semiconductor die with bond pads arranged in an array on an active surface thereof and at least one second semiconductor die with bond pads on an active surface thereof flip-chip connected to bond pads of the first semiconductor device. The at least one second semiconductor die is oriented with the active surface thereof facing the active surface of the first semiconductor die. Corresponding bond pads of the first and at least one second semiconductor dice are connected by placing or forming conductive structures therebetween. A package includes the assembly and a carrier. The first semiconductor die of the assembly is oriented over the carrier with the active surface of the first semiconductor die facing the carrier. Bond pads of the first semiconductor die located laterally beyond an outer periphery of each second semiconductor die are electrically connected to corresponding contacts by way of conductive structures.

Abstract: Structures and methods involving n-channel flash memories with an ultrathin tunnel oxide thickness, have been provided. Both the write and erase operations are performed by tunneling. According to the teachings of the present invention, the n-channel flash memory cell with thin tunnel oxides will operate on a dynamic basis. The stored data can be refreshed every few seconds as necessary. However, the write and erase operations will however now be orders of magnitude faster than traditional n-channel flash memory and the cell provides a large gain. The present invention further provides structures and methods for n-channel floating gate transistors which avoid n-channel threshold voltage shifts and achieve source side tunneling erase. The n-channel memory cell structure includes a floating gate separated from a channel region by an oxide layer of less than 50 Angstroms (Å).

Abstract: The present invention includes a DRAM technology compatible non-volatile, reprogrammable switch formed according to an DRAM optimized process flow. The non-volatile, reprogrammable switch includes a non-volatile memory cell. The non-volatile memory cell includes a first metal oxide semiconductor field effect transistor (MOSFET) formed in a semiconductor substrate. A capacitor is formed in a subsequent layer above the first MOSFET and is separated from the MOSFET by an insulator layer. A vertical electrical via couples a bottom plate of the capacitor through the insulator layer to a gate of first MOSFET. A second MOSFET is formed in the semiconductor substrate. The gate of the first MOSFET also serves as a gate of the second MOSFET. Additional MOSFETs can be combined in a similar fashion with the non-volatile cell to create a new, powerful logic cell that is smaller and more robust than conventional circuit solutions.

Abstract: A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.

Abstract: Current sense amplifiers with hysteresis are provided which conserve scarce chip surface area yet still provide fast response times in a low power CMOS environment. A first embodiment includes a first amplifier and a second amplifier which are electrically coupled. Each amplifier includes a first transistor of a first conductivity type and a second transistor of a second conductivity type, where the first and second transistors are coupled at a drain region. A signal input node is coupled to a source region of the first transistor in each amplifier. A signal output node is coupled to the drain region of the first and the second transistors in the second amplifier. The signal output node is further coupled to a gate of a third transistor in order to introduce hysteresis into the current sense amplifier. Integrated circuits, electrical systems, methods of operation and methods of forming the novel current sense amplifier are similarly included.