Abstract: Additional applications for DRAM technology compatible non-volatile memory cells are presented. The novel applications include the integration of DRAM technology compatible non-volatile memory cells which can be fabricated on a DRAM chip with little or no modification of the DRAM optimized process flow. The novel applications of DRAM technology compatible non-volatile memory cells operate with lower programming voltages than that used by conventional non-volatile memory cells, yet still hold sufficient charge to withstand the effects of parasitic capacitances and noise due to circuit operation. Hence, the requirements of low power densely packed integrated circuits is realized for smaller, portable microprocessor devices. An example of one such application includes a circuit switch.

Abstract: A semiconductor wafer having dice that include circuitry that is placed into a mode when the circuitry receives an alternating signal having certain characteristics. The alternating signal may be supplied from a system controller through a probe, probe pad, and conductive path on the wafer. In a preferred embodiment, the conductive path simultaneously carries a VCC power signal and the alternating signal to the circuitry. However, the alternating signal may be carried on a conductive path different from the one carrying the VCC signal. A great deal of information may be conveyed through the alternating signal, making other signals unnecessary in controlling, testing, stressing, and repairing dice on the wafer. For example, clocking information may be conveyed through the alternating signal. The circuitry may be placed in different modes in response to different characteristics of the alternating signal. The alternating signal and a VCC power signal are received through a single contact on each die.

Abstract: An improved structure and method are provided for increasing the operational bandwidth between different circuit devices, e.g. logic and memory chips, without requiring changes in current CMOS processing techniques. The structure includes the use of a silicon interposer. The silicon interposer can consist of recycled rejected wafers from the front-end semiconductor processing. Micro-machined vias are formed through the silicon interposer. The micro-machined vias include electrical contacts which couple various integrated circuit devices located on the opposing surfaces of the silicon interposer.

Abstract: The present invention includes a DRAM technology compatible non-volatile, reprogrammable switch formed according to an DRAM optimized process flow. The non-volatile, reprogrammable switch includes a non-volatile memory cell. The non-volatile memory cell includes a first metal oxide semiconductor field effect transistor (MOSFET) formed in a semiconductor substrate. A capacitor is formed in a subsequent layer above the first MOSFET and is separated from the MOSFET by an insulator layer. A vertical electrical via couples a bottom plate of the capacitor through the insulator layer to a gate of first MOSFET. A second MOSFET is formed in the semiconductor substrate. The gate of the first MOSFET also serves as a gate of the second MOSFET. Additional MOSFETs can be combined in a similar fashion with the non-volatile cell to create a new, powerful logic cell that is smaller and more robust than conventional circuit solutions.

Abstract: Structures and methods involving n-channel flash memories with an ultrathin tunnel oxide thickness, have been provided. Both the write and erase operations are performed by tunneling. According to the teachings of the present invention, the n-channel flash memory cell with thin tunnel oxides will operate on a dynamic basis. The stored data can be refreshed every few seconds as necessary. However, the write and erase operations will however now be orders of magnitude faster than traditional n-channel flash memory and the cell provides a large gain. The present invention further provides structures and methods for n-channel floating gate transistors which avoid n-channel threshold voltage shifts and achieve source side tunneling erase. The n-channel memory cell structure includes a floating gate separated from a channel region by an oxide layer of less than 50 Angstroms (Å).

Abstract: Novel current sense amplifiers with hysteresis are provided which conserve scarce chip surface area yet still provide fast response times in a low power CMOS environment. A first embodiment includes a first amplifier and a second amplifier which are electrically coupled. Each amplifier includes a first transistor of a first conductivity type and a second transistor of a second conductivity type, where the first and second transistors are coupled at a drain region. A signal input node is coupled to a source region of the first transistor in each amplifier. A signal output node is coupled to the drain region of the first and the second transistor in the second amplifier. The signal output node is further coupled to a gate of a third transistor in order to introduce hysteresis into the current sense amplifier.

Abstract: A memory self-stress mode capable of use during wafer burn-in such as for dynamic random access memory (DRAM) integrated circuits. A burn-in power supply voltage and ground voltage delivered to a common node of a plurality of memory cell storage capacitors and to an equilibrate node coupled to bit lines. An all row high test cycles word lines between a binary low logic level and a binary high logic level, thereby stressing the dielectric of the memory cell storage capacitors by imposing stress voltages of differing polarity. A half row high test cycles alternate word lines of a word line sequence thereby stressing undesired short circuit connections between adjacent word lines.

Abstract: Defective memory is programmed to have a contiguous address space by dividing the logical address space of the memory into a plurality of address sections. The address section containing the address mapped to a defective memory location is identified. The physical memory locations originally mapped to the addresses in the identified address section are remapped to addresses in an address section at one end of the address space. The addresses in the end address section are disabled. Alternatively, spare memory is provided and the addresses in the end address section are remapped to physical locations in the spare memory. A similar remapping procedure is applied to repair defective data paths in a memory. The remapping procedure is applicable to memory devices or memory modules.

Abstract: An on-chip testing device separately locates must-repairs or preferred-repairs in a row direction and column direction of a memory array. A row counter and a column counter are operated to index the memory array in row-major order, and then in column-major order (or vice versa). A running total of the number of failures is kept for each row and column, when the running total equals or exceeds a predetermined value, the row or column is determined to be a must-repair or a preferred repair. Rows to be repaired are substituted with redundant memory rows and-columns-to be prepared are substituted with redundant memory columns.

Abstract: DRAM self-test circuitry performs an on-chip test of a DRAM memory array. The self-test circuitry writes either all ones or all zeroes to each set of physical rows having the same address within the segment to be tested, and then reads the rows a set at a time. If the data bits comprising the set do not all equal one or zero, a resultant error detection signal is generated and used to latch the failed addresses into a failed address queue. If the data bits are either all zeros or ones, the next set of rows are tested. In another embodiment, the self-test circuitry also includes a mechanism for determining the performance of the addressed memory with respect to speed as well as accuracy. When either self-test is complete, the failed addresses stored in the queue may be transmitted to an external, off-chip device or analyzed and acted on by on-chip error correction circuitry.

Abstract: A semiconductor wafer having dice that include circuitry that is placed into a mode when the circuitry receives an alternating signal having certain characteristics. The alternating signal may be supplied from a system controller through a probe, probe pad, and conductive path on the wafer. In a preferred embodiment, the conductive path simultaneously carries a VCC power signal and the alternating signal to the circuitry. However, the alternating signal may be carried on a conductive path different from the one carrying the VCC signal. A great deal of information may be conveyed through the alternating signal, making other signal unnecessary in controlling, testing, stressing, and repairing dice on the wafer. For example, clocking information may be conveyed through the alternating signal. The circuitry may be placed in different modes in response to different characteristics of the alternating signal. The alternating signal and a VCC power signal are received through a single contact on each die.

Abstract: A test arrangement for a memory device wherein the equilibration voltage DVC2 is adjusted up or down relative to a nominal value and coupled to one of the bitlines of the paired bitlines of the memory array, while the equilibrating circuit is held disabled, and then the sense amplifiers are used to pull the bitlines to logic 1 and logic 0 levels initializing the bitlines to test data. Appropriate word lines are fired to copy the test data to some or all of the other rows of the memory array, allowing memory tests to be conducted. In another embodiment, a fixed voltage is applied to one of the bitlines of individual bitlines pairs and the sense amplifiers are used to pull the paired bitlines to the correct voltage. In a further embodiment, fixed voltages Vcc and ground are applied to the bitlines of each bitline pair with the sense amplifier being held disabled. The test arrangement can be implemented as a self-test feature for the memory device.

Abstract: Defective memory is programmed to have a contiguous address space by dividing the logical address space of the memory into a plurality of address sections. The address section containing the address mapped to a defective memory location is identified. The physical memory locations originally mapped to the addresses in the identified address section are remapped to addresses in an address section at one end of the address space. The addresses in the end address section are disabled. Alternatively, spare memory is provided and the addresses in the end address section are remapped to physical locations in the spare memory. A similar remapping procedure is applied to repair defective data paths in a memory. The remapping procedure is applicable to memory devices or memory modules.

Abstract: A test circuit detects defective memory cells in a memory device. The test circuit includes a test mode terminal adapted to receive a test mode signal. An error detection circuit includes a plurality of inputs and an output, each input coupled to some of the plurality of memory cells. The error detection circuit develops an active error signal on an output when the binary value of data on at least one input is different from predetermined binary values of data. A control circuit is coupled to the test mode terminal, the error detection circuit, and the memory cells. The control circuit is operable responsive to the test mode signal being active to apply the data of accessed memory cells to the associated inputs of the error detection circuit such that the error detection circuit drives the error signal active when the binary value of the data stored in at least one accessed memory cell is different from predetermined binary values.

Abstract: An on-chip testing device separately locates must-repairs or preferred-repairs in a row direction and column direction of a memory array. A row counter and a column counter are operated to index the memory array in row-major order, and then in column-major order (or vice versa). A running total of the number of failures is kept for each row and column, when the running total equals or exceeds a predetermined value, the row or column is determined to be a must-repair or a preferred repair.

Abstract: A method of testing a memory array is disclosed, the method comprising writing a test pattern to the memory array in as few as one or two RAS cycles by first activating the input/output data lines and then selectively activating multiple rows and columns. The method can be used with a variety of test environments. For example, the disclosed method may be implemented in testing using automated test equipment, and may also be incorporated in devices having built-in self-test circuitry. The disclosed method reduces the time required to test the memory array with minimal additional circuitry and no encroachment on valuable die real estate.

Abstract: A memory circuit is described which includes memory cells for storing data. The memory circuit can be read from or written to by an external system such as a microprocessor or core logic chip set. The microprocessor provides memory cell address data to the memory circuit and can request that data be output on communication lines for reading therefrom. The memory circuit reduces the time needed to read data stored in the memory by providing a valid output data signal. The valid output data signal indicates that data coupled to the communication lines has stabilized and is therefore valid. Different valid output data signals and trigger circuits for producing the signals are described.

Abstract: A semiconductor wafer having dice that include circuitry that is placed into a mode when the circuitry receives an alternating signal having certain characteristics. The alternating signal may be supplied from a system controller through a probe, probe pad, and conductive path on the wafer. In a preferred embodiment, the conductive path simultaneously carries a VCC power signal and the alternating signal to the circuitry. However, the alternating signal may be carried on a conductive path different from the one carrying the VCC signal. A great deal of information may be conveyed through the alternating signal, making other signals unnecessary in controlling, testing, stressing, and repairing dice on the wafer. For example, clocking information may be conveyed through the alternating signal. The circuitry may be placed in different modes in response to different characteristics of the alternating signal. The alternating signal and a VCC power signal are received through a single contact on each die.

Abstract: A memory circuit is described which has an output data strobe signal that indicates when valid data is available on the output lines. Several alternate signals and circuits are described which can be used for the output strobe signal. An echo clock signal is described which selectively follows an input clock signal in a synchronous memory system and indicated when valid output data is available. The output strobe signal is used to speed the reading of data from the output line by allowing a microprocessor, or other external circuit, to read the data from the output lines as soon as it is valid, thereby eliminating the need to wait a specified period of time.

Abstract: A semiconductor wafer having dice that include circuitry that is placed into a mode when the circuitry receives an alternating signal having certain characteristics. The alternating signal may be supplied from a system controller through a probe, probe pad, and conductive path on the wafer. In a preferred embodiment, the conductive path simultaneously carries a VCC power signal and the alternating signal to the circuitry. However, the alternating signal may be carried on a conductive path different from the one carrying the VCC signal. A great deal of information may be conveyed through the alternating signal, making other signals unnecessary in controlling, testing, stressing, and repairing dice on the wafer. For example, clocking information may be conveyed through the alternating signal. The circuitry may be placed in different modes in response to different characteristics of the alternating signal. The alternating signal and a VCC power signal are received through a single contact on each die.