Abstract: A semiconductor device, including a substrate, a first source/drain region, a second source/drain region, and a gate structure, is provided. The substrate has an extra body portion and a fin protruding from a top surface of the substrate, wherein the fin spans the extra body portion. The first source/drain region and the second source/drain region are in the fin. The gate structure spans the fin, is located above the extra body portion, and is located between the first source/drain region and the second source/drain region.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first metal layer over a substrate, forming a dielectric layer over the first metal layer. The method includes forming a trench in the dielectric layer, and performing a surface treatment process on a sidewall surface of the trench to form a hydrophobic layer. The hydrophobic layer is formed on a sidewall surface of the dielectric layer. The method further includes depositing a metal material in the trench and over the hydrophobic layer to form a via structure.

Abstract: A transistor includes an insulating layer, a source region, a drain region, a channel layer, a ferroelectric layer, and a gate electrode. The source region and the drain region are respectively disposed on and in physical contact with two opposite sidewalls of the insulating layer. A thickness of the source region, a thickness of the drain region, and a thickness of the insulating layer are substantially the same. The channel layer is disposed on the insulating layer, the source region, and the drain region. The ferroelectric layer is disposed over the channel layer. The gate electrode is disposed on the ferroelectric layer.

Abstract: The invention provides a hydrophilized polydiorganosiloxane vinylic crosslinker which comprises (1) a polydiorganosiloxane polymer chain comprising dimethylsiloxane units and hydrophilized siloxane units each having one methyl substituent and one monovalent C4-C40 organic radical substituent having two to six hydroxyl groups, wherein the molar ratio of the hydrophilized siloxane units to the dimethylsiloxane units is from about 0.035 to about 0.15, and (2) two terminal (meth)acryloyl groups. The hydrophilized polydiorganosiloxane vinylic crosslinker has a number average molecular weight of from about 3000 Daltons to about 80,000 Daltons. The present invention is also related to a silicone hydrogel contact lens, which comprises repeating units derived from a hydrophilized polydiorganosiloxane vinylic crosslinker of the invention.

Abstract: The present disclosure provides a semiconductor wafer. The semiconductor wafer includes: a scribe line between a first row of dies and a second row of dies; and a benchmark circuit disposed adjacent to the scribe line and electrically coupled to a first conductive contact and a second conductive contact. The benchmark circuit includes a first device-under-test (DUT); a second DUT; a first switching circuit configured to selectively couple the first DUT and the second DUT to the first conductive contact; and a second switching circuit configured to selectively couple the first DUT and the second DUT to the second conductive contact.

Abstract: The present disclosure provides a semiconductor device and a method for forming a semiconductor device. The semiconductor device includes a substrate, and a first gate dielectric stack over the substrate, wherein the first gate dielectric stack includes a first ferroelectric layer, and a first dielectric layer coupled to the first ferroelectric layer, wherein the first ferroelectric layer includes a first portion made of a ferroelectric material in orthorhombic phase, a second portion made of the ferroelectric material in monoclinic phase, and a third portion made of the ferroelectric material in tetragonal phase, wherein a total volume of the second portion is greater than a total volume of the first portion, and the total volume of the first portion is greater than a total volume of the third portion.

Abstract: A method includes the following operations: disconnecting at least one of drain regions that are formed on a first active area, of first transistors, from a first voltage; and disconnecting at least one of drain regions that are formed on a second active area, of second transistors coupled to the first transistors from a second voltage. The at least one of drain regions of the second transistors corresponds to the at least one of drain regions of the first transistors.

Abstract: An information handling system includes a host processing system and a Liquid Crystal Display device. The host processing system includes a graphics processing unit (GPU) and the LCD device includes a memory device and a DisplayPort Configuration Data (DPCD) register. The host processing system 1) determines whether the first GPU supports a Dynamic Display Shifting (DDS) mode, 2) when the GPU does not support the DDS mode, provides a first indication to the LCD device that the GPU does not support the DDS mode, and 3) when the GPU supports the DDS mode, provides a second indication to the LCD device that the GPU supports the DDS mode. The LCD device retrieves a Panel Self Refresh (PSR) setting from the memory device and stores the PSR setting to the DPCD register in response to the first indication, and retrieves a DDS setting from the memory and stores the DDS setting to the DPCD register in response to the second indication.

Abstract: A semiconductor device includes a first set of nanostructures stacked over a substrate in a vertical direction, and each of the first set of nanostructures includes a first end portion and a second end portion, and a first middle portion laterally between the first end portion and the second end portion. The first end portion and the second end portion are thicker than the first middle portion. The semiconductor device also includes a first plurality of semiconductor capping layers around the first middle portions of the first set of nanostructures, and a gate structure around the first plurality of semiconductor capping layers.

Abstract: A memory device includes a substrate, a bottom electrode disposed over the substrate, a top electrode disposed over the bottom electrode, and a phase change layer disposed between the top electrode and bottom electrode. The phase change layer includes a GeSbTe material that contains a Ge content of about 20 at % or less, a Sb content of about 30 at % or more, and a Te content of about 40 at % at or more.

Abstract: An apparatus in an overhead transport system is provided. The apparatus includes a hanger feature configured to be hung from a ceiling, a plate-like structure having a top surface and a bottom surface, the bottom surface being rotatably coupled to the hanger feature, and at least one pair of rail members mechanically coupled to the bottom surface of the plate-like structure by way of a plurality of yoke members.

Abstract: The present disclosure provides a multi-state one-time programmable (MSOTP) memory circuit including a memory cell and a programming voltage driving circuit. The memory cell includes a MOS storage transistor, a first MOS access transistor and a second MOS access transistor electrically connected to store two bits of data. When the memory cell is in a writing state, the programming voltage driving circuit outputs a writing control potential to the gate of the MOS storage transistor, and when the memory cell is in a reading state, the programming voltage driving circuit outputs a reading control potential to the gate of the MOS storage transistor.

Abstract: A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate; forming source/drain regions over the fin on opposing sides of the gate structure; forming a first dielectric layer and a second dielectric layer successively over the source/drain regions; performing a first etching process to form an opening in the first dielectric layer and in the second dielectric layer, where the opening exposes an underlying electrically conductive feature; after performing the first etching process, performing a second etching process to enlarge a lower portion of the opening proximate to the substrate; and forming a contact plug in the opening after the second etching process.

Abstract: A semiconductor device includes a first to sixth regions, a first gate, a first metal contact and a second metal contact. The second region is disposed opposite to the first region with respect to the first gate. The first metal contact couples the first region to the second region. The fourth region is disposed opposite to the third region with respect to the first gate. The second metal contact is coupling the third region to the fourth region. The fifth region is disposed between the first gate and the second region, and is disconnected from the first metal contact and the second metal contact. The sixth region is disposed between the first gate and the first region, and is disconnected from the first metal contact and the second metal contact.

Abstract: A support frame includes first and second mounting members, and an adjusting member. The second mounting member defines a groove. One groove wall of the groove defines a plurality of positioning holes. The adjusting member includes a base body, a sliding member, and an elastic member. The base body is disposed on the first mounting member, and at least a part of the base body is accommodated in the groove. The sliding member is slidably disposed on the base body and includes a clamping body. The elastic member is disposed on the sliding member, and the elastic member can drive the sliding member to engage the clamping body with one of the plurality of positioning holes. When the support frame is in a cabinet, an interior installation size of the cabinet is adjustable for any particular relative position between the first and second mounting members.

Abstract: The present invention provides a multi-directional multi-joint turning piece and a display device including the multi-directional multi-joint turning piece. The multi-directional multi-joint turning piece is configured to connect a first display module and a second display module to provide a first display module unfolded or folded with the second display module. The multi-directional multi-joint turning piece includes a first coupling piece, a first turning piece, a second turning piece, a third turning piece, and a second coupling piece, wherein the first coupling piece is connected to the first display module, the second coupling piece is connected to the second display module, the first coupling piece is pivoted to the first turning piece, the first turning piece is pivoted to the second turning piece, the second turning piece is pivoted to the third turning piece, and the third turning piece is pivoted to the second coupling piece.

Abstract: One-time programmable (OTP) bit-cell for an integrated circuit (IC) that includes an OTP element, such as a fuse or antifuse, coupled in electrical series with a selector that comprises a Schottky junction. The selector may comprise a metal-semiconductor-metal (MSM) material stack operable as transient voltage suppression (TVS) device that experiences electrical breakdown at a voltage below a programming voltage of the OTP element. In response to a programming voltage, the MSM stack may breakdown and pass a transient current sufficient for programming the OTP element. In response to a lower (e.g., read) voltage, the MSM stack may breakdown and pass a transient current insufficient for programming, but sufficient to sense a state of the OTP element. In response to an even lower (e.g., half-read) voltage, the MSM stack may present a very high OTP bit-cell input impedance, reducing leakage and/or sneak path currents within an array of such bit-cells.

Abstract: Semiconductor structures and methods are provided. A method according to the present disclosure includes providing a workpiece that includes a plurality of active regions including channel regions and source/drain regions, and a plurality of dummy gate stacks intersecting the plurality of active regions at the channel regions, the plurality of dummy gate stacks including a device portion and a terminal end portion. The method further includes depositing a gate spacer layer over the workpiece, anisotropically etching the workpiece to recess the source/drain regions and to form a gate spacer from the gate spacer layer, forming a patterned photoresist layer over the workpiece to expose the device portion and the recessed source/drain regions while the terminal end portion is covered, and after the forming of the patterned photoresist layer, epitaxially forming source/drain features over the recessed source/drain regions.

Abstract: An array of poly lines on an active device area of an integrated chip is extended to form a dummy device structure on an adjacent isolation region. The resulting dummy device structure is an array of poly lines having the same line width, line spacing, and pitch as the array of poly lines on the active device area. The poly lines of the dummy device structure are on grid with the poly lines on the active device area. Because the dummy device structure is formed of poly lines that are on grid with the poly lines on the active device area, the dummy device structure may be much closer to the active device area than would otherwise be possible. The resulting proximity of the dummy device structure to the active device area improves anti-dishing performance and reduces empty space on the integrated chip.

Abstract: The present disclosure, in some embodiments, relates to a method of developing a photosensitive material. The method includes forming a photosensitive material over a substrate. The photosensitive material is exposed to electromagnetic radiation focused at a plurality of different heights over the substrate. The plurality of different heights are vertically separated from one another and are disposed within the photosensitive material along a vertical path that extends in a direction perpendicular to an upper surface of the photosensitive material. The photosensitive material is developed to remove a soluble region.