Abstract: A memory device includes a substrate, a bottom electrode disposed over the substrate, a top electrode disposed over the bottom electrode, and a phase change layer disposed between the top electrode and bottom electrode. The phase change layer includes a GeSbTe material that contains a Ge content of about 20 at % or less, a Sb content of about 30 at % or more, and a Te content of about 40 at % at or more.

Abstract: An apparatus in an overhead transport system is provided. The apparatus includes a hanger feature configured to be hung from a ceiling, a plate-like structure having a top surface and a bottom surface, the bottom surface being rotatably coupled to the hanger feature, and at least one pair of rail members mechanically coupled to the bottom surface of the plate-like structure by way of a plurality of yoke members.

Abstract: The present disclosure provides a multi-state one-time programmable (MSOTP) memory circuit including a memory cell and a programming voltage driving circuit. The memory cell includes a MOS storage transistor, a first MOS access transistor and a second MOS access transistor electrically connected to store two bits of data. When the memory cell is in a writing state, the programming voltage driving circuit outputs a writing control potential to the gate of the MOS storage transistor, and when the memory cell is in a reading state, the programming voltage driving circuit outputs a reading control potential to the gate of the MOS storage transistor.

Abstract: A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate; forming source/drain regions over the fin on opposing sides of the gate structure; forming a first dielectric layer and a second dielectric layer successively over the source/drain regions; performing a first etching process to form an opening in the first dielectric layer and in the second dielectric layer, where the opening exposes an underlying electrically conductive feature; after performing the first etching process, performing a second etching process to enlarge a lower portion of the opening proximate to the substrate; and forming a contact plug in the opening after the second etching process.

Abstract: A semiconductor device includes a first to sixth regions, a first gate, a first metal contact and a second metal contact. The second region is disposed opposite to the first region with respect to the first gate. The first metal contact couples the first region to the second region. The fourth region is disposed opposite to the third region with respect to the first gate. The second metal contact is coupling the third region to the fourth region. The fifth region is disposed between the first gate and the second region, and is disconnected from the first metal contact and the second metal contact. The sixth region is disposed between the first gate and the first region, and is disconnected from the first metal contact and the second metal contact.

Abstract: A support frame includes first and second mounting members, and an adjusting member. The second mounting member defines a groove. One groove wall of the groove defines a plurality of positioning holes. The adjusting member includes a base body, a sliding member, and an elastic member. The base body is disposed on the first mounting member, and at least a part of the base body is accommodated in the groove. The sliding member is slidably disposed on the base body and includes a clamping body. The elastic member is disposed on the sliding member, and the elastic member can drive the sliding member to engage the clamping body with one of the plurality of positioning holes. When the support frame is in a cabinet, an interior installation size of the cabinet is adjustable for any particular relative position between the first and second mounting members.

Abstract: The present invention provides a multi-directional multi-joint turning piece and a display device including the multi-directional multi-joint turning piece. The multi-directional multi-joint turning piece is configured to connect a first display module and a second display module to provide a first display module unfolded or folded with the second display module. The multi-directional multi-joint turning piece includes a first coupling piece, a first turning piece, a second turning piece, a third turning piece, and a second coupling piece, wherein the first coupling piece is connected to the first display module, the second coupling piece is connected to the second display module, the first coupling piece is pivoted to the first turning piece, the first turning piece is pivoted to the second turning piece, the second turning piece is pivoted to the third turning piece, and the third turning piece is pivoted to the second coupling piece.

Abstract: One-time programmable (OTP) bit-cell for an integrated circuit (IC) that includes an OTP element, such as a fuse or antifuse, coupled in electrical series with a selector that comprises a Schottky junction. The selector may comprise a metal-semiconductor-metal (MSM) material stack operable as transient voltage suppression (TVS) device that experiences electrical breakdown at a voltage below a programming voltage of the OTP element. In response to a programming voltage, the MSM stack may breakdown and pass a transient current sufficient for programming the OTP element. In response to a lower (e.g., read) voltage, the MSM stack may breakdown and pass a transient current insufficient for programming, but sufficient to sense a state of the OTP element. In response to an even lower (e.g., half-read) voltage, the MSM stack may present a very high OTP bit-cell input impedance, reducing leakage and/or sneak path currents within an array of such bit-cells.

Abstract: Semiconductor structures and methods are provided. A method according to the present disclosure includes providing a workpiece that includes a plurality of active regions including channel regions and source/drain regions, and a plurality of dummy gate stacks intersecting the plurality of active regions at the channel regions, the plurality of dummy gate stacks including a device portion and a terminal end portion. The method further includes depositing a gate spacer layer over the workpiece, anisotropically etching the workpiece to recess the source/drain regions and to form a gate spacer from the gate spacer layer, forming a patterned photoresist layer over the workpiece to expose the device portion and the recessed source/drain regions while the terminal end portion is covered, and after the forming of the patterned photoresist layer, epitaxially forming source/drain features over the recessed source/drain regions.

Abstract: An array of poly lines on an active device area of an integrated chip is extended to form a dummy device structure on an adjacent isolation region. The resulting dummy device structure is an array of poly lines having the same line width, line spacing, and pitch as the array of poly lines on the active device area. The poly lines of the dummy device structure are on grid with the poly lines on the active device area. Because the dummy device structure is formed of poly lines that are on grid with the poly lines on the active device area, the dummy device structure may be much closer to the active device area than would otherwise be possible. The resulting proximity of the dummy device structure to the active device area improves anti-dishing performance and reduces empty space on the integrated chip.

Abstract: The present disclosure, in some embodiments, relates to a method of developing a photosensitive material. The method includes forming a photosensitive material over a substrate. The photosensitive material is exposed to electromagnetic radiation focused at a plurality of different heights over the substrate. The plurality of different heights are vertically separated from one another and are disposed within the photosensitive material along a vertical path that extends in a direction perpendicular to an upper surface of the photosensitive material. The photosensitive material is developed to remove a soluble region.

Abstract: A loop antenna which has a signal input/output wire, a first conductor, an upper conductor, an upper conductor, a second conductor, a first lower conductor, and a second lower conductor sequentially connected. The loop antenna further has a first grounding via, and a lower end of the first grounding via is connected to a first grounding layer, and an upper end of the first grounding via is disposed between and connecting the first lower conductor and the second lower conductor, wherein a first end of the second lower conductor is connected to the upper end of the first grounding via, and a second end of the second lower conductor is connected to the first conductor. A second grounding layer and the combination of the signal input/output wire, the first lower conductor, and the second lower conductor are disposed on the same layer disconnectedly.

Abstract: An electrical connector includes a socket, a plug and a locking component. The socket includes a socket case having a fixing groove disposed at the outer surface and a socket terminal configured in the socket case. The plug includes a plug case having a locking hole, a containing space configured for containing the socket case and a plug terminal configured in the containing space. The locking component is disposed in the locking hole and configured to move in the locking hole. When the plug is connected to the socket, the socket terminal embeds into the plug terminal, so that the socket case is located between the plug case and the plug terminal and the fixing groove is corresponding to the locking hole. Then, the locking component moves toward the plug terminal and engages to the fixing groove to lock the plug and the socket.

Abstract: A power plug device includes a first housing, a circuit board, a wire assembly and a second housing. The first housing includes an upper-housing body, a through hole and an inner cover. An accommodating portion is arranged in the upper-housing body, the through hole is formed on one side of the upper-housing body, the inner cover is installed in the accommodating portion, a receptive space is arranged in the inner cover, and the through hole interconnects with the receptive space. The wire assembly includes core wires, which passes through the through hole and the receptive space, so that the core wires are accommodated in the accommodating portion, and the receptive space is suitable for accommodating glue to secure the core wires and provides waterproof effect. In addition, dual-layered waterproof structure is used to make the first and second housing joining together having stronger waterproof effect.

Abstract: Electrostatic discharge (ESD) structures are provided. An ESD structure includes a semiconductor substrate, a first epitaxy region with a first type of conductivity over the semiconductor substrate, a second epitaxy region with a second type of conductivity over the semiconductor substrate, and a plurality of first semiconductor layers and a plurality of second semiconductor layers. The first and second semiconductor layers are alternatingly stacked over the semiconductor substrate and between the first and second epitaxy regions. A first conductive feature is formed over the first epitaxy region and outside an oxide diffusion region. A second conductive feature is formed over the second epitaxy region and outside the oxide diffusion region. The oxide diffusion region is disposed between the first and second conductive features.

Abstract: Semiconductor structures and methods are provided. A method according to the present disclosure includes providing a workpiece that includes a plurality of active regions including channel regions and source/drain regions, and a plurality of dummy gate stacks intersecting the plurality of active regions at the channel regions, the plurality of dummy gate stacks including a device portion and a terminal end portion. The method further includes depositing a gate spacer layer over the workpiece, anisotropically etching the workpiece to recess the source/drain regions and to form a gate spacer from the gate spacer layer, forming a patterned photoresist layer over the workpiece to expose the device portion and the recessed source/drain regions while the terminal end portion is covered, and after the forming of the patterned photoresist layer, epitaxially forming source/drain features over the recessed source/drain regions.

Abstract: A loop antenna which has a signal input/output wire, a first conductor, an upper conductor, an upper conductor, a second conductor, a first lower conductor, and a second lower conductor sequentially connected. The loop antenna further has a first grounding via, and a lower end of the first grounding via is connected to a first grounding layer, and an upper end of the first grounding via is disposed between and connecting the first lower conductor and the second lower conductor, wherein a first end of the second lower conductor is connected to the upper end of the first grounding via, and a second end of the second lower conductor is connected to the first conductor. A second grounding layer and the combination of the signal input/output wire, the first lower conductor, and the second lower conductor are disposed on the same layer disconnectedly.

Abstract: A method includes the following operations: disconnecting at least one of drain regions that are formed on a first active area, of first transistors, from a first voltage; and disconnecting at least one of drain regions that are formed on a second active area, of second transistors coupled to the first transistors from a second voltage. The at least one of drain regions of the second transistors corresponds to the at least one of drain regions of the first transistors.

Abstract: A circuit board assembly in a camera module for blocking unwanted light when images are captured includes a circuit board, a sensor, and an optical blocking body connecting the circuit board and the sensor. The circuit board includes a base board and a photomask. The photomask is arranged on a surface of the base board, the base board includes conductive circuit layers and dielectric layers, the conductive circuit layers and the dielectric layers are alternately arranged, the sensor being electronically connected to the conductive layers. The optical blocking body, the photomask, and the dielectric layers block ambient light entering the camera module other than through the lens assembly of the camera module.