Abstract: This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.

Abstract: A body layer is formed in an epitaxial layer and a gate electrode formed in a trench in the body and epitaxial layer. A gate insulator is disposed along a sidewall of the gate electrode between the gate electrode and the source, between the gate electrode and the P-body and between the gate electrode and the epitaxial layer. A cap insulator is disposed on top of the gate electrode. A doped spacer is disposed along a sidewall of the source and a sidewall of the gate insulator. The body layer next to the polysilicon spacer is etched back below the bottom of the polysilicon spacer. Dopants are diffused from the spacer to form the source region.

Abstract: A copper bonding compatible bond pad structure and associated method is disclosed. The device bond pad structure includes a buffering structure formed of regions of interconnect metal and regions of non-conductive passivation material, the buffering structure providing buffering of underlying layers and structures of the device.

Abstract: A top-side cooled semiconductor package with stacked interconnection plate is disclosed. The semiconductor package includes a circuit substrate with terminal leads, a semiconductor die atop the circuit substrate, a low thermal resistance intimate interconnection plate for bonding and interconnecting a top contact area of the semiconductor die with the circuit substrate, a low thermal resistance stacked interconnection plate atop the intimate interconnection plate for top-side cooling, a molding encapsulant for encapsulating the package except for exposing a top surface of the stacked interconnection plate to maintain effective top-side cooling. The top portion of the stacked interconnection plate can include a peripheral overhang above the intimate interconnection plate. The peripheral overhang allows for a maximized exposed top surface area for heat dissipation independent of otherwise areal constraints applicable to the intimate interconnection plate.

Abstract: This invention discloses a semiconductor power device disposed on a semiconductor substrate includes a plurality of deep trenches with an epitaxial layer filling said deep trenches and a simultaneously grown top epitaxial layer covering areas above a top surface of said deep trenches over the semiconductor substrate. A plurality of trench MOSFET cells disposed in said top epitaxial layer with the top epitaxial layer functioning as the body region and the semiconductor substrate acting as the drain region whereby a super-junction effect is achieved through charge balance between the epitaxial layer in the deep trenches and regions in the semiconductor substrate laterally adjacent to the deep trenches. Each of the trench MOSFET cells further includes a trench gate and a gate-shielding dopant region disposed below and substantially aligned with each of the trench gates for each of the trench MOSFET cells for shielding the trench gate during a voltage breakdown.

Abstract: Power wafer level chip scale package (CSP) and process of manufacture are enclosed. The power wafer level chip scale package includes all source, gate and drain electrodes located on one side of the device, which is convenient for mounting to a printed circuit board (PCB) with solder paste.

Abstract: A semiconductor device includes a gate electrode, a top source region disposed next to the gate electrode, a drain region disposed below the bottom of the gate electrode, a oxide disposed on top of the source region and the gate electrode, and a doped polysilicon spacer disposed along a sidewall of the source region and a sidewall of the oxide. Methods for manufacturing such device are also disclosed. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: A method and structure for a semiconductor device, the device including a handle wafer, a diamond layer formed directly on a front side of the handle wafer, and a thick oxide layer formed directly on a back side of the handle wafer, the oxide layer of a thickness to counteract tensile stresses of the diamond layer. Nitride layers are formed on outer surfaces of the diamond layer and thick oxide layer and a polysilicon is formed on outer surfaces of the nitride layers. A device wafer is bonded to the handle wafer to form the semiconductor device.

Abstract: A system according to an embodiment of the present invention includes one or more first optical sensors and one or more second optical sensors. The first optical sensor(s) each include a photodetector region and a plurality of first slats over the photodetector region. The second optical sensor(s) each include a photodetector region and a plurality of second slats over the photodetector region, wherein the second slats have a different configuration than the first slats. For example, the second slats can be orthogonal relative to the first slats. For another example, the first slats can slant in a first direction, and the second slats can slant in a second direction generally opposite the first direction. Currents produced by the first optical sensor(s) and the second optical sensor(s), which are indicative of light incident on the optical sensors, are useful for distinguishing between movement in at least two different directions.

Abstract: Exemplary embodiments provide structures and methods for power devices with integrated clamp structures. The integration of clamp structures can protect the power device, e.g., from electrical overstress (EOS). In one embodiment, active devices can be formed over a substrate, while a clamp structure can be integrated outside the active regions of the power device, for example, under the active regions and/or inside the substrate. Integrating clamp structure outside active regions of power devices can maximize the active area for a given die size and improve robustness of the clamped device since the current will spread in the substrate by this integration.

Abstract: A body layer is formed in an epitaxial layer and a gate electrode formed in a trench in the body and epitaxial layer. A gate insulator is disposed along a sidewall of the gate electrode between the gate electrode and the source, between the gate electrode and the P-body and between the gate electrode and the epitaxial layer. A cap insulator is disposed on top of the gate electrode. A doped spacer is disposed along a sidewall of the source and a sidewall of the gate insulator. The body layer next to the polysilicon spacer is etched back below the bottom of the polysilicon spacer. Dopants are diffused from the spacer to form the source region.

Abstract: Monolithic optical sensor devices, and methods for fabricating such devices, are described herein. In an embodiment, a semiconductor wafer substrate includes a plurality of photodetector (PD) regions. A wafer-level inorganic dielectric optical filter is deposited and thereby formed over at least a subset of the plurality of PD regions. One or more wafer-level organic color filter(s) is/are deposited and thereby formed on one or more selected portion(s) of the wafer-level inorganic dielectric optical filter that is/are over selected ones of the PD regions. For example, an organic red filter, an organic green filter and an organic blue filter can be over, respectively, portions of the wafer-level inorganic dielectric optical filter that are over first, second and third PD regions.

Abstract: A power semiconductor device package includes a conductive assembly including a connecting structure and a semiconductor die having an aperture formed therethrough, the aperture being sized and configured to spacedly receive the connecting structure. In an alternative embodiment, a power semiconductor device package includes a conductive assembly including a connecting structure and a pair of semiconductor die disposed on either side of the connecting structure in spaced relationship thereto.

Abstract: A voltage converter includes an output circuit having a high side device and a low side device which can be formed on a single die (i.e. a “PowerDie”) and connected to each other through a semiconductor substrate. Both the high side device and the low side device can include lateral diffused metal oxide semiconductor (LDMOS) transistors. Because both output transistors include the same type of transistors, the two devices can be formed simultaneously, thereby reducing the number of photomasks over other voltage converter designs. The voltage converter can further include a controller circuit on a different die which can be electrically coupled to, and co-packaged with, the PowerDie.

Abstract: Light sensors including dielectric optical coatings to shape their spectral responses, and methods for fabricating such light sensors in a manner that accelerates lift-off processes and increases process margins, are described herein. In certain embodiments, a short duration soft bake is performed. Alternatively, or additionally, temperature cycling is performed. Alternatively, or additionally, photolithography is performed using a photomask that includes one or more dummy corners, dummy islands and/or dummy rings. Each of the aforementioned embodiments form and/or increase a number of micro-cracks in the dielectric optical coating not covering the photodetector sensor region, thereby enabling an accelerated lift-off process and an increased process margin. Alternatively, or additionally, a portion of the photomask can include chamfered corners so that the dielectric optical coating includes chamfered corners, which improves the thermal reliability of the dielectric optical coating.

Abstract: Light sensors including dielectric optical coatings to shape their spectral responses, and methods for fabricating such light sensors in a manner that accelerates lift-off processes and increases process margins, are described herein. In certain embodiments, a short duration soft bake is performed. Alternatively, or additionally, temperature cycling is performed. Alternatively, or additionally, photolithography is performed using a photomask that includes one or more dummy corners, dummy islands and/or dummy rings. Each of the aforementioned embodiments form and/or increase a number of micro-cracks in the dielectric optical coating not covering the photodetector sensor region, thereby enabling an accelerated lift-off process and an increased process margin. Alternatively, or additionally, a portion of the photomask can include chamfered corners so that the dielectric optical coating includes chamfered corners, which improves the thermal reliability of the dielectric optical coating.

Abstract: A power converter can include an output circuit having a high-side device and a low-side device which can be formed on a single die (a “PowerDie”). The power converter can further include a controller integrated circuit (IC) formed on a different die which can be electrically coupled to, and co-packaged with, the PowerDie. The PowerDie can be attached to a die pad of a leadframe, and the controller IC die can be attached to an active surface of the first die such that the first die is interposed between the controller IC die and the die pad.

Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of deep trenches. The deep trenches are filled with an epitaxial layer thus forming a top epitaxial layer covering areas above a top surface of the deep trenches covering over the semiconductor substrate. The semiconductor power device further includes a plurality of transistor cells disposed in the top epitaxial layer whereby a device performance of the semiconductor power device is dependent on a depth of the deep trenches and not dependent on a thickness of the top epitaxial layer. Each of the plurality of transistor cells includes a trench DMOS transistor cell having a trench gate opened through the top epitaxial layer and filled with a gate dielectric material.

Abstract: A solder-top enhanced semiconductor device is proposed for packaging. The solder-top device includes a device die with a top metal layer patterned into contact zones and contact enhancement zones. At least one contact zone is electrically connected to at least one contact enhancement zone. Atop each contact enhancement zone is a solder layer for an increased composite thickness thus lowered parasitic impedance. Where the top metal material can not form a uniform good electrical bond with the solder material, the device die further includes an intermediary layer sandwiched between and forming a uniform electrical bond with the top metal layer and the solder layer. A method for making the solder-top device includes lithographically patterning the top metal layer into the contact zones and the contact enhancement zones; then forming a solder layer atop each of the contact enhancement zones using a stencil process for an increased composite thickness.

Abstract: A method and structure for a voltage converter including a trench field effect transistor (FET) and a trench guarded Schottky diode which is integrated with the trench FET. In an embodiment, a voltage converter can include a lateral FET, a trench FET, and a trench guarded Schottky diode integrated with the trench FET. A method to form a voltage converter can include the formation of a trench FET gate, a trench guarded Schottky diode gate, and a lateral FET gate using a single conductive layer such as a polysilicon layer.