Abstract: A semiconductor device includes a via structure penetrating through a substrate, a top metal layer and an electronic component over the via structure, and a bottom metal layer and another electronic component below the via structure. The via structure includes a through hole penetrating from a first surface to an opposite second surface of a substrate, a filling insulating layer within the through hole, a first conductive layer, which is within the through hole and surrounds the filling insulating layer, wherein a portion of the first conductive layer is below the filling insulating layer and at the bottom of the through hole. The via structure further includes a first insulating layer, which is on the sidewalls of the through hole and surrounds the first conductive layer.

Abstract: A vertical Hall sensor, a Hall sensor module, and a method for manufacturing the same are provided. By applying a trench structure inside a substrate with respect to a ground terminal, a directional component parallel to surface of the substrate is maximized with respect to a current flow to detect the magnetic field with improved sensitivity.

Abstract: This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.

Abstract: Provided are a low-cost semiconductor device manufacturing method and a semiconductor device made using the method. The method includes forming multiple body regions in a semiconductor substrate, forming multiple gate insulating layers and multiple gate electrodes in the body region; implementing a blanket ion implantation in an entire surface of the substrate to form a low concentration doping region (LDD region) in the body region without a mask, forming a spacer at a side wall of the gate electrode, and implementing a high concentration ion implantation to form a high concentration source region and a high concentration drain region around the LDD region. According to the examples, devices have favorable electrical characteristics and at the same time, manufacturing costs are reduced. Since, when forming high concentration source region and drain regions, tilt and rotation co-implants are applied, an LDD masking step is potentially omitted.

Abstract: A lateral bipolar transistor includes trench emitter and trench collector regions to form ultra-narrow emitter regions, thereby improving emitter efficiency. The same trench process is used to form the emitter/collector trenches as well as the trench isolation structures so that no additional processing steps are needed to form the trench emitter and collector. In embodiments of the present invention, the trench emitter and trench collector regions may be formed using ion implantation into trenches formed in a semiconductor layer. In other embodiments, the trench emitter and trench collector regions may be formed by out-diffusion of dopants from heavily doped polysilicon filled trenches.

Abstract: A humidity sensor and a method of manufacturing the same are provided where voids are formed within interconnects configured to facilitate the operation of the device and a humidity sensing material is deposited within the voids to detect the humidity. The accuracy with respect to the measurement of the humidity sensor is improved and manufacturing costs are lowered. The humidity sensor includes a substrate, a first interlayer insulating layer disposed on the substrate, first and second metal electrodes disposed adjacent to each other on the first interlayer insulating layer, an etch stop layer covering the first interlayer insulating layer and the first and second metal electrodes, a second interlayer insulating layer disposed on the first etch stop layer, voids formed within the second interlayer insulating layer, and a humidity sensing material deposited in the voids.

Abstract: Provided is a semiconductor power device. The semiconductor power device includes a well disposed in a substrate, a gate overlapping the well, a source region disposed at one side of the gate, a buried layer disposed in the well, and a drain region or a drift region contacting the buried layer.

Abstract: A semiconductor device with voids within a silicon-on-insulator (SOI) structure and a method of forming the semiconductor device are provided. Voids are formed within a Buried Oxide layer (BOX layer) of the silicon-on-insulator (SOI) semiconductor to enhance a performance index of an RF-SOI switch. The semiconductor device with voids within a silicon-on-insulator (SOI) structure includes a semiconductor substrate; an insulating layer disposed on the substrate; a silicon-on-insulator (SOI) layer disposed on the insulating layer; a device isolation layer and an active area disposed within the SOI layer; one or more voids disposed within the insulating layer; and a sealing insulating sealing an opening of the void.

Abstract: This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.

Abstract: A lateral bipolar transistor includes trench emitter and trench collector regions to form ultra-narrow emitter regions, thereby improving emitter efficiency. The same trench process is used to form the emitter/collector trenches as well as the trench isolation structures so that no additional processing steps are needed to form the trench emitter and collector. In embodiments of the present invention, the trench emitter and trench collector regions may be formed using ion implantation into trenches formed in a semiconductor layer. In other embodiments, the trench emitter and trench collector regions may be formed by out-diffusion of dopants from heavily doped polysilicon filled trenches.

Abstract: Provided are a low-cost semiconductor device manufacturing method and a semiconductor device made using the method. The method includes forming multiple body regions in a semiconductor substrate, forming multiple gate insulating layers and multiple gate electrodes in the body region; implementing a blanket ion implantation in an entire surface of the substrate to form a low concentration doping region (LDD region) in the body region without a mask, forming a spacer at a side wall of the gate electrode, and implementing a high concentration ion implantation to form a high concentration source region and a high concentration drain region around the LDD region. According to the examples, devices have favorable electrical characteristics and at the same time, manufacturing costs are reduced. Since, when forming high concentration source region and drain regions, tilt and rotation co-implants are applied, an LDD masking step is potentially omitted.

Abstract: The present disclosure relates to a vertical bipolar junction transistor. A vertical bipolar junction transistor includes a high concentration doping region emitter terminal disposed on a semiconductor substrate; a high concentration doping region collector terminal disposed on a semiconductor substrate; a high concentration doping region base terminal disposed between the emitter terminal and the collector terminal; a drift region having a first doping concentration surrounding the emitter terminal and being deeper than either the base terminal or the collector terminal; a base layer disposed below the drift region; a collector layer in contact with the base layer, the collector layer having a second doping concentration higher than the first doping concentration. The manufacturing cost of the vertical bipolar junction transistor can be lowered and a current gain can be elevated using a low-cost BCD process.

Abstract: Provided is a semiconductor package. The semiconductor package includes: a first die that is a monolithic type die, a driver circuit and a low-side output power device formed in the first die; a second die disposed above the first die, the second die comprising a high-side output power device; and a first connection unit disposed between the first die and the second die.

Abstract: Provided is a semiconductor package. The semiconductor package includes: a first die that is a monolithic type die, a driver circuit and a low-side output power device formed in the first die; a second die disposed above the first die, the second die comprising a high-side output power device; and a first connection unit disposed between the first die and the second die.

Abstract: Embodiments disclosed herein provide for a circuit including first die having an active side and a backside, wherein the first die is flip-chip mounted to a carrier. The circuit also includes a second die stacked on the backside of the first die, wherein the second die is stacked on the first die such that a backside of the second die is facing the backside of the first die and an active side of the second die faces away from the first die.

Abstract: The present disclosure relates to a photo sensor module. The thickness and size of an IC chip may be reduced by manufacturing a photo sensor based on a semiconductor substrate and improving the structure to place a UV sensor on the upper section of an active device or a passive device. The photo sensor module includes a semiconductor substrate, a field oxide layer, formed on the semiconductor substrate, and a photo sensor comprising a photo diode formed on the field oxide layer.

Abstract: The present disclosure relates to a photo sensor module. The thickness and size of an IC chip may be reduced by manufacturing a photo sensor based on a semiconductor substrate and improving the structure to place a UV sensor on the upper section of an active device or a passive device. The photo sensor module includes a semiconductor substrate, a field oxide layer, formed on the semiconductor substrate, and a photo sensor comprising a photo diode formed on the field oxide layer.

Abstract: Embodiments disclosed herein provide for a circuit including first die having an active side and a backside, wherein the first die is flip-chip mounted to a carrier. The circuit also includes a second die stacked on the backside of the first die, wherein the second die is stacked on the first die such that a backside of the second die is facing the backside of the first die and an active side of the second die faces away from the first die.

Abstract: A semiconductor device with an embedded schottky diode and a manufacturing method thereof are provided. A semiconductor device having a schottky diode include: an epilayer of a first conductivity type, a body layer of a second conductivity type, and a source layer of the first conductivity type arranged in that order; a gate trench that extends from the source layer to a part of the epilayer; a body trench formed a predetermined distance from the gate trench and extends from the source layer to a part of the epilayer; and a guard ring of the second conductivity type that contacts an outer wall of the body trench and formed in the epilayer.

Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of deep trenches. The deep trenches are filled with an epitaxial layer thus forming a top epitaxial layer covering areas above a top surface of the deep trenches covering over the semiconductor substrate. The semiconductor power device further includes a plurality of transistor cells disposed in the top epitaxial layer whereby a device performance of the semiconductor power device is dependent on a depth of the deep trenches and not dependent on a thickness of the top epitaxial layer. Each of the plurality of transistor cells includes a trench DMOS transistor cell having a trench gate opened through the top epitaxial layer and filled with a gate dielectric material.