Abstract: The PPG based NIBG neural network prediction system of the present invention comprises a neural network configured to predict BG level of a subject based on PPG signal obtained from the subject wherein the subject is not undergoing medical treatment and the neural network is trained using training data from subjects not undergoing medical treatment. In another embodiment, the PPG based NIBG neural network prediction system of the present invention predicts BG level of a subject based on HbA1c of the subject measured using conventional finger prick method as well as PPG signal obtained from the subject wherein the subject is not undergoing medical treatment and the neural network is trained using training data from subjects not undergoing medical treatment.

Abstract: An external counter pulsation system (ECP) and method for using the system to improve circulation as well as cardiovascular related diseases. The ECP system of the present invention comprises a helical air bladder for modulating blood flow of major veins and arteries of the thigh. High efficiency is realized with the helical shape of the air bladder to lower the cost, weight and size of the ECP of the present invention.

Abstract: An external counter pulsation system (ECP) and method for using the system to improve circulation as well as cardiovascular related diseases. The ECP system of the present invention comprises a helical air bladder for modulating blood flow of major veins and arteries of the thigh. High efficiency is realized with the helical shape of the air bladder to lower the cost, weight and size of the ECP of the present invention.

Abstract: An integrated circuit structure includes a semiconductor substrate; a diode; and a phase change element over and electrically connected to the diode. The diode includes a first doped semiconductor region of a first conductivity type, wherein the first doped semiconductor region is embedded in the semiconductor substrate; and a second doped semiconductor region over and adjoining the first doped semiconductor region, wherein the second doped semiconductor region is of a second conductivity type opposite the first conductivity type.

Abstract: An integrated circuit structure includes a semiconductor substrate; a diode; and a phase change element over and electrically connected to the diode. The diode includes a first doped semiconductor region of a first conductivity type, wherein the first doped semiconductor region is embedded in the semiconductor substrate; and a second doped semiconductor region over and adjoining the first doped semiconductor region, wherein the second doped semiconductor region is of a second conductivity type opposite the first conductivity type.

Abstract: An integrated circuit structure includes a semiconductor substrate; a diode; and a phase change element over and electrically connected to the diode. The diode includes a first doped semiconductor region of a first conductivity type, wherein the first doped semiconductor region is embedded in the semiconductor substrate; and a second doped semiconductor region over and adjoining the first doped semiconductor region, wherein the second doped semiconductor region is of a second conductivity type opposite the first conductivity type.

Abstract: FinFET devices, along with methods for fabricating such devices, are disclosed herein for facilitating device characterization. An exemplary FinFET device includes a fin having a first portion extending in a first direction and a second portion extending from the first portion in a second direction. The second direction is substantially perpendicular to the first direction. The first portion includes a first region doped with a first type dopant disposed between second regions doped with a second type dopant. The first type dopant is opposite the second type dopant. A source contact and a drain contact are coupled to the second regions of the first portion, and a body contact is coupled to the second portion. A gate is disposed over the first region of the first portion, and the second portion extends from the first region.

Abstract: A semiconductor structure includes a semiconductor substrate comprising a PMOS region and an NMOS region; a PMOS device in the PMOS region; and an NMOS device in the NMOS region. The PMOS device includes a first gate stack on the semiconductor substrate; a first offset spacer on a sidewall of the first gate stack; a stressor in the semiconductor substrate and adjacent to the first offset spacer; and a first raised source/drain extension region on the stressor and adjoining the first offset spacer, wherein the first raised source/drain extension region has a higher p-type dopant concentration than the stressor.

Abstract: FinFET devices, along with methods for fabricating such devices, are disclosed herein for facilitating device characterization. An exemplary FinFET device includes a fin having a first portion extending in a first direction and a second portion extending from the first portion in a second direction. The second direction is substantially perpendicular to the first direction. The first portion includes a first region doped with a first type dopant disposed between second regions doped with a second type dopant. The first type dopant is opposite the second type dopant. A source contact and a drain contact are coupled to the second regions of the first portion, and a body contact is coupled to the second portion. A gate is disposed over the first region of the first portion, and the second portion extends from the first region.

Abstract: A bio-chip adapted for separating and concentrating particles in a solution includes a chip body defining a receiving space therein for receiving the solution, an inner electrode disposed in the receiving space, an outer electrode unit disposed in the receiving space of the chip body and including a first outer electrode that is spaced apart from and surrounds the inner electrode, and a second outer electrode that is spaced apart from and surrounds the first outer electrode, and a power source electrically connected to the inner electrode, the first outer electrode, and the second outer electrode. A method for using the bio-chip to separating and concentrating the particles in the solution is also disclosed in the present invention.

Abstract: A method and system is disclosed for providing access to the body of a FinFET device. In one embodiment, a FinFET device for characterization comprises an active fin comprising a source fin, a depletion fin, and a drain fin; a side fin extending from the depletion fin and coupled to a body contact for providing access for device characterization; and a gate electrode formed over the depletion fin and separated therefrom by a predetermined dielectric layer, wherein the gate electrode and the dielectric layer thereunder have a predetermined configuration to assure the source and drain fins are not shorted.

Abstract: An integrated circuit structure includes a semiconductor substrate; a diode; and a phase change element over and electrically connected to the diode. The diode includes a first doped semiconductor region of a first conductivity type, wherein the first doped semiconductor region is embedded in the semiconductor substrate; and a second doped semiconductor region over and adjoining the first doped semiconductor region, wherein the second doped semiconductor region is of a second conductivity type opposite the first conductivity type.

Abstract: An integrated circuit structure includes a semiconductor substrate; a diode; and a phase change element over and electrically connected to the diode. The diode includes a first doped semiconductor region of a first conductivity type, wherein the first doped semiconductor region is embedded in the semiconductor substrate; and a second doped semiconductor region over and adjoining the first doped semiconductor region, wherein the second doped semiconductor region is of a second conductivity type opposite the first conductivity type.

Abstract: A memory device includes a phase change element, which further includes a first phase change layer having a first grain size; and a second phase change layer over the first phase change layer. The first and the second phase change layers are depth-wise regions of the phase change element. The second phase change layer has a second average grain size different from the first average grain size.

Abstract: A method of fabricating a memory cell includes forming a bottom electrode on a substrate, a variable resistive material layer on the bottom electrode, and a top electrode on the variable resistive material layer. A first metal oxide layer interposes the top electrode and the variable resistive material layer. In an embodiment, the first metal oxide layer is a self-formed layer provided by the oxidation of a portion of the top electrode. In an embodiment, a second metal oxide layer is provided interposing the first metal oxide layer and the variable resistive material layer. The second metal oxide may be a self-formed layer formed by the reduction of the variable resistive material layer.

Abstract: A key mechanism for a saxophone includes a lever, a sound-hole cover, an adjustment member, and a touch piece. The lever includes a connecting portion in which being formed a rotation-stop hole, and a slot in communication with and perpendicular to the rotation-stop hole. The adjustment member is rotatably and partially disposed in the slot and has a threaded hole in communication with the rotation-stop hole. The touch piece includes a press portion, a rotation-stop portion and a screw. The rotation-stop portion is engaged in the rotation-shaped hole, and the screw is screwed in the threaded hole of the adjustment member, so that rotating the adjustment member causes the screw to linearly move with respect to the adjustment member. Therefore, the height position of touch piece of the saxophone can be adjusted without using any hand tools.

Abstract: A key mechanism for a saxophone includes a lever, a sound-hole cover, an adjustment member, and a touch piece. The lever includes a connecting portion in which being formed a rotation-stop hole, and a slot in communication with and perpendicular to the rotation-stop hole. The adjustment member is rotatably and partially disposed in the slot and has a threaded hole in communication with the rotation-stop hole. The touch piece includes a press portion, a rotation-stop portion and a screw. The rotation-stop portion is engaged in the rotation-shaped hole, and the screw is screwed in the threaded hole of the adjustment member, so that rotating the adjustment member causes the screw to linearly move with respect to the adjustment member. Therefore, the height position of touch piece of the saxophone can be adjusted without using any hand tools.

Abstract: The present invention relates to a method for fabricating FinFETs and the structure thereof. The present invention uses an additional mask to define regions forming semiconductor fins having high semiconductor-fin height. By making use of multiple etching processes of the insulating layer, structures with differences in the height of semiconductor fins are achieved. The method can be combined with current process for semiconductor-based FinFETs for overcoming effectively the problem of electron-channel-width quantization effect as well as improving the performance of FinFETs.

Abstract: An integrated circuit comprises a substrate and a buried dielectric formed in the substrate. The buried dielectric has a first thickness in a first region, a second buried dielectric thickness in a second region, and a step between the first and second regions. A semiconductor layer overlies the buried dielectric.

Abstract: A method for forming a semiconductor device and a device made using the method are provided. In one example, the method includes forming a hard mask layer on a semiconductor substrate and patterning the hard mask layer to form multiple openings. The substrate is etched through the openings to form forming a plurality of trenches separating multiple semiconductor mesas. The trenches are partially filled with a dielectric material. The hard mask layer is removed and multiple-gate features are formed, with each multiple-gate feature being in contact with a top surface and sidewalls of at least one of the semiconductor mesas.