Abstract: Two local buffers are provided between an image processing unit and an image compression and expansion unit for compression into a predetermined format. Write and read control units serve to alternately use the two local buffers. As a result, process flow starting from the image processing unit to generate compressed image data by the image compression and expansion unit requires no main memory, whereby high-speed image processing is allowed with low power consumption.

Abstract: Two local buffers are provided between an image processing unit and an image compression and expansion unit for compression into a predetermined format. Write and read control units serve to alternately use the two local buffers. As a result, process flow starting from the image processing unit to generate compressed image data by the image compression and expansion unit requires no main memory, whereby high-speed image processing is allowed with low power consumption.

Abstract: Two local buffers are provided between an image processing unit and an image compression and expansion unit for compression into a predetermined format. Write and read control units serve to alternately use the two local buffers. As a result, process flow starting from the image processing unit to generate compressed image data by the image compression and expansion unit requires no main memory, whereby high-speed image processing is allowed with low power consumption.

Abstract: The least significant bits of respective count values of an H counter and a V counter are combined, to generate a timing signal defining a 2×2-size repeat block. A timing register including four registers each storing data which determines a color of each location within the repeat block is provided for each of input channels. A selector selects one of outputs of the timing registers based on the timing signal, and generates a signal designating a color of a pixel at a certain time for each of the input channels. A register storing black level correction data for each color is used in common by the input channels. For each of the input channels, an item of black level correction data at the certain time is selected based on the signal designating the color of the pixel at the certain time and input to a pre-processing circuit in each of the input channels.

Abstract: An image processing apparatus includes a first storage section and a second storage section, a storage control section, and a computation section. The storage control section sequentially acquires block images obtained as a result of dividing an input image, and stores the block image as a target block image in the first storage section, while storing, in the second storage section, image data of, in a region of the target block image, a region abutting un-inputted block images in the input image, as image data of an abuttal region. The computation section implements a resizing process for changing the size of the target block image by performing an interpolation calculation using image data of the target block image stored in the first storage section and the image data of the abuttal region stored in the second storage section.

Abstract: An image processing unit includes a computing unit, a data input unit that inputs image data to the computing unit, a data output unit that outputs the image data computed by the computing unit, and a setting unit. The computing unit includes computing cells including multiple types of computing cells, input domain selectors, and at least one of output domain selectors. The setting unit sets the input domain selectors and the output domain selectors so that image data inputted by the data input unit to the computing unit on which desired computing has been performed by at least one computing cell among the computing cells is outputted from the data output unit.

Abstract: In a memory device, data can be transmitted from a first CPU to a second CPU via an individual register or a shared SRAM, for example. The data transmitted from the first CPU to the second CPU via the individual register also passes through a FIFO. When first data is transmitted via the shared SRAM and then second data is transmitted via the individual register, for example, and if the first data transmission is adjusted by a SRAM controller and put into a waiting state at the FIFO, the second data transmitted via the individual register also passes through the FIFO, preventing the second data transmission from being completed earlier than the first data transmission. The data transmissions can therefore be completed appropriately. This in turn increases reliability of the memory device.

Abstract: Two local buffers are provided between an image processing unit and an image compression and expansion unit for compression into a predetermined format. Write and read control units serve to alternately use the two local buffers. As a result, process flow starting from the image processing unit to generate compressed image data by the image compression and expansion unit requires no main memory, whereby high-speed image processing is allowed with low power consumption.

Abstract: Scanning image data and target image data are respectively stored in a first storage area and a second storage area. In one case, (J?M+1)×(K?N+1)×M×N pieces of pixel data are stored as comparison image data relating to all comparison areas, and M×N pieces of pixel data are stored as target image data. In contrast, the present invention requires the storage only of J×K pieces of pixel data as scanning image data, and M×N pieces of pixel data as target image data. This means the number of pieces of pixel data to be stored is reduced. In the case discussed above, one piece of target image data and (J?M+1)×(K?N+1) pieces of pixel data relating to all comparison areas and corresponding to this target image data are stored. As compared to this case, the number of times pixel data are retrieved is reduced to 1/(M×N), thereby shortening processing speed.

Abstract: OSD data YD includes a color designating signal As and a color changing signal Ex. When a color register number is designated by the color designating signal As, a color storage unit 41 outputs an appropriate color signal. A Y signal is branched from the outputted color signal and subjected to a modulating process by the color changing signal Ex. The Y changing signal obtained by the modulating process is merged with a Cb signal and a Cr signal so as to form new color signal. The OSD data YD with changed color is subjected to a synthesizing process with image data XD according to the predetermined mixture ratio.

Abstract: First pixel data of a pixel of interest is output from a first shift register, while second and third pixel data of neighboring pixels indicative of the same color are output from second and third shift registers, respectively. Differential data between estimated pixel data calculated from the second and third pixel data and the first pixel data is input to a comparator. A threshold value stored in a register is modulated by the estimated pixel data, and is input to the comparator as modulated threshold data. When the comparator judges that the differential data is greater than the modulated threshold data, a selector outputs the estimated pixel data as corrected pixel data.

Abstract: An image processing apparatus is provided which offers higher versatility than conventional image processing apparatuses. When an input signal to a spatial filtering block is a monochrome signal that contains Y component only, a selector selects its input terminal and a selector selects its input terminal. Then, a low-pass filter output signal of a programmable spatial filter is inputted to a spatial filter, and a low-pass filter output signal of the spatial filer is inputted to a spatial filter. That is, the programmable spatial filter and the spatial filters are connected in series (in cascade), and the cascade-connected three spatial filters perform filtering operation. In this example, low-pass filters with 5×5 taps are connected in cascade in three stages, which enables low-pass filtering with 13×13 taps.

Abstract: An image processing apparatus is provided which offers higher versatility than conventional image processing apparatuses. When an input signal to a spatial filtering block is a monochrome signal that contains Y component only, a selector selects its input terminal and a selector selects its input terminal. Then, a low-pass filter output signal of a programmable spatial filter is inputted to a spatial filter, and a low-pass filter output signal of the spatial filer is inputted to a spatial filter. That is, the programmable spatial filter and the spatial filters are connected in series (in cascade), and the cascade-connected three spatial filters perform filtering operation. In this example, low-pass filters with 5×5 taps are connected in cascade in three stages, which enables low-pass filtering with 13×13 taps.

Abstract: An image processing apparatus includes: a relative coordinate acquisition part acquiring a corresponding position on an input image with respect to a predetermined pixel on an output image; a first storage part storing position information of the corresponding position; a reading control part causing pixel values of input pixels on the input image to be sequentially read; an organization part organizing a set of grid points formed of input pixels among input pixels read by the reading control part; a judgment part judging, based on the position information, whether or not pixel values of pixels in the vicinity of the corresponding position used in calculating a pixel value of the predetermined pixel have been read; a local memory storing, in a case where judgment is made that pixels in the vicinity of the corresponding position have been read, pixel values of pixels forming the set of grid points as pixel values of surrounding pixels regarding the predetermined pixel; and a pixel value calculation part calcul

Abstract: The first frame of captured image data is stored as raw data in a main memory, and parameters for exposure control and white balance control are calculated from the stored image data and are set in the RPU. The second and subsequent frames of captured image data are processed in real time in the RPU without being stored in the main memory after being output from a CCD. The second and subsequent frames of captured image data are subjected to exposure control, white balance control, and JPEG compression, and then, are stored in the main memory. After operations for continuously capturing images are finished, the raw data corresponding to the first frame stored in the main memory is read by the RPU, where exposure control and white balance control are performed, and then, is stored as JPEG data in the main memory.

Abstract: First pixel data of a pixel of interest is output from a first shift register, while second and third pixel data of neighboring pixels indicative of the same color are output from second and third shift registers, respectively. Differential data between estimated pixel data calculated from the second and third pixel data and the first pixel data is input to a comparator. A threshold value stored in a register is modulated by the estimated pixel data, and is input to the comparator as modulated threshold data. When the comparator judges that the differential data is greater than the modulated threshold data, a selector outputs the estimated pixel data as corrected pixel data.

Abstract: A motion detecting part detects moving regions in a plurality of frame images captured by rolling shutter type exposure, and obtains a motion vector of the moving regions. A moving region correcting part corrects the moving region in a to-be-corrected frame image of the plurality of frame images on the basis of the motion vector, information on an image-capturing time interval between the plurality of frame images, information on an exposure starting time difference resulting from the difference in position in one frame image caused by the rolling shutter type exposure and information on an exposure start sequence depending on the position in one frame image captured by the rolling shutter type exposure.

Abstract: First pixel data of a pixel of interest is output from a first shift register, while second and third pixel data of neighboring pixels indicative of the same color are output from second and third shift registers, respectively. Differential data between estimated pixel data calculated from the second and third pixel data and the first pixel data is input to a comparator. A threshold value stored in a register is modulated by the estimated pixel data, and is input to the comparator as modulated threshold data. When the comparator judges that the differential data is greater than the modulated threshold data, a selector outputs the estimated pixel data as corrected pixel data.

Abstract: When a compression part outputs JPEG data which is discrete in the time direction, the valid data is accumulated in an FIFO. When the valid data of predetermined size is accumulated in the FIFO, an encapsulation part adds markers before and after the valid data and transmits JPEG stream data to a host control module. This stream data includes encapsulated data in which the valid data is encapsulated with the markers and invalid data. The host control module stores this stream data in an SDRAM without any change. Then, by searching data for the markers, the valid data is acquired and the JPEG data is reproduced.

Abstract: RGB image data outputted from an ADC (3) is processed in an SPU (42) and an RPU (43) and then buffered into a memory (48) as YUV image data. The YUV image data is outputted from a YUV output unit (45), encoded by an image compression and expansion chip (5A) and transmitted to a main chip (4) by a DMAC (52). On the other hand, compressed moving image data stored in the memory (48) is transmitted to the image compression and expansion chip (5A) through the control by a DMAC (44), decoded therein, then converted into RGB image data in an RGB sampling unit (54) and inputted to the main chip (4) by the SPU (42) through a data line (14). With such a construction, it is possible to provide a circuit for compression and expansion, which allows connection with a main processing chip having no YUV input circuit without increasing circuit scale, maintaining general versatility of those circuits.