Patents by Inventor Gen Sasaki

Gen Sasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070177026
    Abstract: The least significant bits of respective count values of an H counter and a V counter are combined, to generate a timing signal defining a 2×2-size repeat block. A timing register including four registers each storing data which determines a color of each location within the repeat block is provided for each of input channels. A selector selects one of outputs of the timing registers based on the timing signal, and generates a signal designating a color of a pixel at a certain time for each of the input channels. A register storing black level correction data for each color is used in common by the input channels. For each of the input channels, an item of black level correction data at the certain time is selected based on the signal designating the color of the pixel at the certain time and input to a pre-processing circuit in each of the input channels.
    Type: Application
    Filed: January 26, 2007
    Publication date: August 2, 2007
    Applicant: MegaChips LSI Solutions Inc.
    Inventor: Gen SASAKI
  • Patent number: 7249893
    Abstract: A rolling bearing and a rod end bearing are provided with a tilt mechanism and a rotary mechanism that are mutually independent. The tilt mechanism has a non-lubricated type spherical sliding bearing structure. The rotary mechanism has a rolling bearing structure which may or may not be sealed. By means of the non-lubricated type spherical sliding bearing structure, a tilt of the shaft center is made possible, and by means of a sealed rolling bearing structure, problems such as a lubrication oil leak are avoided, and carrying out high speed rotation and continuous rotation become possible. Because the sealed rolling bearing structure of the rotary mechanism does not call for a shaft center tilt function at all, the material of the seal can be chosen such that it emphasizes sliding resistance and high durability.
    Type: Grant
    Filed: February 21, 2003
    Date of Patent: July 31, 2007
    Assignee: Minebea Co. Ltd
    Inventors: Gen Sasaki, Shinichi Akao, Makoto Fujino
  • Publication number: 20070147706
    Abstract: A similar-image detecting part detects similar image regions similar to one another in a plurality of frame images captured by rolling shutter type exposure. A displacement-vector detecting part detects a displacement vector of each of the similar image regions with respect to a reference position in each of the plurality of frame images. An average calculating part calculates an average of displacement vectors in the plurality of frame images. A correcting part shifts a similar image region in one of the plurality of frame images such that the displacement vector of the similar image region becomes the average calculated by the average calculating part.
    Type: Application
    Filed: December 20, 2006
    Publication date: June 28, 2007
    Applicant: MegaChips LSI Solutions Inc.
    Inventors: Gen SASAKI, Yusuke Nara
  • Publication number: 20070120997
    Abstract: A motion detecting part detects moving regions in a plurality of frame images captured by rolling shutter type exposure, and obtains a motion vector of the moving regions. A moving region correcting part corrects the moving region in a to-be-corrected frame image of the plurality of frame images on the basis of the motion vector, information on an image-capturing time interval between the plurality of frame images, information on an exposure starting time difference resulting from the difference in position in one frame image caused by the rolling shutter type exposure and information on an exposure start sequence depending on the position in one frame image captured by the rolling shutter type exposure.
    Type: Application
    Filed: November 16, 2006
    Publication date: May 31, 2007
    Applicant: MegaChips LSI Solutions Inc.
    Inventors: Gen Sasaki, Yusuke Nara
  • Patent number: 7224397
    Abstract: A CPU performs a control for photographing a main subject in absence of auxiliary light, whereby an image signal is outputted from an analogue signal processing section. Next, the CPU performs a control for photographing the main subject in presence of the auxiliary light, whereby an image signal is outputted from the analogue signal processing section. An AF area extracting section extracts image signals in an AF area from the image signals. A differential signal calculating section outputs a differential signal between the extracted image signal, and a distance measuring section compares magnitudes of that differential signal and a reference value in a distance data base to calculate distance information based on the comparison result. An AF control section executes AF control of mountain climbing system with the use of the distance information.
    Type: Grant
    Filed: August 28, 2002
    Date of Patent: May 29, 2007
    Assignee: Mega Chips Corporation
    Inventor: Gen Sasaki
  • Publication number: 20070098273
    Abstract: When a compression part outputs JPEG data which is discrete in the time direction, the valid data is accumulated in an FIFO. When the valid data of predetermined size is accumulated in the FIFO, an encapsulation part adds markers before and after the valid data and transmits JPEG stream data to a host control module. This stream data includes encapsulated data in which the valid data is encapsulated with the markers and invalid data. The host control module stores this stream data in an SDRAM without any change. Then, by searching data for the markers, the valid data is acquired and the JPEG data is reproduced.
    Type: Application
    Filed: September 21, 2006
    Publication date: May 3, 2007
    Applicant: MegaChips LSI Solutions Inc.
    Inventor: Gen SASAKI
  • Patent number: 7206021
    Abstract: A hybrid pixel interpolating apparatus (1) has a function of converting raw image data (D1) having one color component for each pixel into pixel interpolated data in which each pixel has a plurality of color components. This hybrid pixel interpolating apparatus (1) includes: a register (2) for holding pixel data in a predetermined pixel region in the raw image data (D1) to be inputted; a plurality of pixel interpolating parts (41, 42, . . . , 4n?1, 4n (n: integer not less than 2)) for sampling pixel data (D2) inputted from the register (2) to execute a pixel interpolating process; and a mixing coefficient calculating part (3) for calculating mixing coefficients (?1, ?2, . . . , ?n), and also includes a mixing part (5) for fetching and mixing interpolated data (DI1, DI2, . . . , DIn) outputted from the respective pixel interpolating parts (41 to 4n) to output the resultant.
    Type: Grant
    Filed: February 12, 2003
    Date of Patent: April 17, 2007
    Assignee: Mega Chips Corporation
    Inventors: Gen Sasaki, Takashi Matsutani
  • Patent number: 7196729
    Abstract: The present invention provides an AF evaluation value calculating device in which speed of AF control does not deteriorate even when a number of AF areas are set. The AF evaluation value calculating device for calculating an AF evaluation value used for AF (auto-focus) control of a digital camera, includes: at least one AF evaluation value calculating unit 13 for calculating an AF evaluation value in each of a plurality of AF areas which are set in an image area of image data supplied; and a data transmitter (17a and ch0) for transmitting the AF evaluation value calculated by the AF evaluation value calculator 13 into a predetermined memory by DMA (Direct Memory Access).
    Type: Grant
    Filed: February 12, 2003
    Date of Patent: March 27, 2007
    Assignee: Mega Chips Corporation
    Inventor: Gen Sasaki
  • Patent number: 7190396
    Abstract: In image input devices such as digital still cameras, processing is speeded up and power consumption is reduced by arranging in a RPU (23) performing real time processing of a pixel data from a CCD (21), such that only special exceptional image processing not being prepared previously is subjected to a software program processing in a CPU (24) and, in post processing in which a general image processing is carried out, a pixel data temporarily stored in a main memory (29) is inputted again to the RPU (23) and then processed. This enables to sharply speed up processing, and minimize a prolonged processing in the CPU (24) to reduce power consumption, when compared to the case of executing by software problem processing.
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: March 13, 2007
    Assignee: Mega Chips Corporation
    Inventor: Gen Sasaki
  • Patent number: 7184604
    Abstract: It is an object of the present invention to prevent an image distortion from occurring by using a line memory of small memory capacity. For example, an image is decomposed into strip regions 12, and each strip region 12 is filtered together with certain excess data 14 from a neighboring strip region 12 to prevent an image distortion from occurring at the boundary between the strip regions 12 while executing band decomposition on the strip region 12 which is smaller in size than the entire image with a smaller line memory. In the band decomposition, a line memory which supports band decomposition of, for example, 3 decomposition levels is repeatedly and recursively used, whereby band decomposition of deeper decomposition levels is executed without any problems. In this manner, line-based wavelet transform for deeper decomposition levels is executed with a small line memory. Also reverse wavelet transform is executed in the similar manner.
    Type: Grant
    Filed: February 25, 2003
    Date of Patent: February 27, 2007
    Assignee: Mega Chips Corporation
    Inventors: Yusuke Mizuno, Gen Sasaki
  • Publication number: 20060257680
    Abstract: A copper foil 1 comprises a roughened plating layer 2, a Ni—Co alloy plating layer 3, a zinc galvanized (underlying) layer 4, a chromate treatment layer 5, and a silane coupling treatment layer 6 on a surface to be bonded with a base material for a printed circuit board, and the chromate treatment layer 5 is formed by using a trivalent chromium conversion treatment solution containing 70 mg/L or more and less than 500 mg/L of trivalent chromium ions converted into metal chromium and having a pH-value of 3.0 to 4.5. According to the present invention, a copper foil for a printed circuit board, a method for fabricating the same, and a trivalent chromium conversion treatment solution used for fabricating the same, which have an excellent controllability in Zn film forming amount and chromate film forming amount can be obtained.
    Type: Application
    Filed: October 14, 2005
    Publication date: November 16, 2006
    Inventors: Muneo Kodaira, Shingo Watanabe, Gen Sasaki, Yasuyuki Ito, Katsumi Nomura
  • Publication number: 20060256213
    Abstract: In image input devices such as digital still cameras, processing is speeded up and power consumption is reduced by arranging in a RPU (23) performing real time processing of a pixel data from a CCD (21), such that only special exceptional image processing not being prepared previously is subjected to a software program processing in a CPU (24) and, in post processing in which a general image processing is carried out, a pixel data temporarily stored in a main memory (29) is inputted again to the RPU (23) and then processed. This enables to sharply speed up processing, and minimize a prolonged processing in the CPU (24) to reduce power consumption, when compared to the case of executing by software problem processing.
    Type: Application
    Filed: July 21, 2006
    Publication date: November 16, 2006
    Applicant: MEGA CHIPS CORPORATION
    Inventor: Gen Sasaki
  • Patent number: 7116358
    Abstract: In image input devices such as digital still cameras, processing is speeded up and power consumption is reduced by arranging in a RPU (23) performing real time processing of a pixel data from a CCD (21), such that only special exceptional image processing not being prepared previously is subjected to a software program processing in a CPU (24) and, in post processing in which a general image processing is carried out, a pixel data temporarily stored in a main memory (29) is inputted again to the RPU (23) and then processed. This enables to sharply speed up processing, and minimize a prolonged processing in the CPU (24) to reduce power consumption, when compared to the case of executing by software problem processing.
    Type: Grant
    Filed: December 13, 1999
    Date of Patent: October 3, 2006
    Assignee: Mega Chips Corporation
    Inventor: Gen Sasaki
  • Publication number: 20060192859
    Abstract: Concerning increasingly downsized electronic devices equipped with cameras, an object of the present invention is to achieve easy adaptability of parts. A camera module includes an image sensor and a flash memory, and a main module includes an image processing unit and an SDRAM, and the two modules are connected through a flexible cable. The flash memory stores an image processing program for controlling the image processing unit. The image processing program is a program adapted for the camera module. The flash memory also stores adjustment data that is peculiar to the camera module. When the camera function is turned on, the program is downloaded to the main module and image processing is performed.
    Type: Application
    Filed: February 8, 2006
    Publication date: August 31, 2006
    Applicant: MegaChips LSI Solutions Inc.
    Inventor: Gen SASAKI
  • Patent number: 7034868
    Abstract: A pixel clock is switched to a high speed for reading culled pixel data from a CCD or switched to a low speed for reading all pixels from the CCD when picking up an image of an object, so that a main memory stores a first field initially read from the CCD and an RPU reads the first field from the main memory in synchronization with reading of a subsequent second field for executing a series of image processing in real time. The main memory stores the processed data. A CPU reads the processed data from the main memory, compresses the processed data and thereafter stores the same in a storage medium. Thus provided is an image processing circuit capable of increasing a frame rate for finder display and efficiently executing image processing at a high speed.
    Type: Grant
    Filed: November 2, 2001
    Date of Patent: April 25, 2006
    Assignee: Mega Chips Corporation
    Inventor: Gen Sasaki
  • Patent number: 6992708
    Abstract: A signal processing circuit is provided which can perform high-speed image rotation, reflection, and the like, by such a configuration that an image input apparatus, e.g., a digital still camera, has a coprocessor connected to a CPU; the coprocessor has register groups (RG1 to RG4) which are electrically connected one another, each register group having registers (R1 to R4) of 32 bits length; and the registers (R1 to R4) store a one-byte image data in the zero-th to third bytes, respectively. When an image data read from the CPU to the register group (RG3) is transferred to the register group (RG1) through the register group (RG2), the image can be rotated 90 degrees counterclockwise. Also, other processing such as a clockwise 90 degrees rotation, symmetrical reflection in horizontal direction, etc. can be conducted at a high speed, without converting the data length of an image data.
    Type: Grant
    Filed: February 15, 2000
    Date of Patent: January 31, 2006
    Assignee: Mega Chips Corporation
    Inventor: Gen Sasaki
  • Publication number: 20060007353
    Abstract: An image conversion device is provided with a first buffer area for storing either one of even field and odd field of inputted dot sequential data and a second buffer area for storing the other thereof. A data transfer control circuit controls in such a manner that, during a period in which one of the two fields is written in the first buffer area, the other field, stored in the second buffer area, is read out in a color field sequential format, and during a period in which the other field is written in the second buffer area, the other field, stored in the first buffer area, is read out in a color field sequential format. A pixel interpolating circuit carries out an insertion-interpolating process on the field read out from the image storing unit, and outputs the resulting data. Thus, it becomes possible to prevent color breaking at the time of displaying motion images on a color field sequential type display by using a buffer area having a capacity of one frame.
    Type: Application
    Filed: September 15, 2005
    Publication date: January 12, 2006
    Applicant: MEGA CHIPS CORPORATION
    Inventors: Takashi Matsutani, Gen Sasaki
  • Patent number: 6967660
    Abstract: To enable a brightness histogram operation without requiring a special-purpose integration circuit and memory. An image processing apparatus is provided with a gamma correction processing part. The gamma correction processing part 6 includes a LUT operation circuit 10 having a LUT memory 11 for gamma correction, a simplified gamma correction circuit 12, selectors 14 and 15, and a register 13. When the gamma correction processing part 6 is used exclusively for gamma correction, the CPU 3 makes the register 13 hold aw control signal of L level to thereby cause the selectors 14 and 15 to select “0” terminals. The LUT memory 11 selects and outputs a gamma correction value (LUT conversion value) while referring to input pixel data as address data. On the other hand, when the gamma correction processing part 6 is used for brightness histogram operation, the CPU 3 makes the register 13 hold a control signal of H level to thereby cause the selectors 14 and 15 to select “1” terminals.
    Type: Grant
    Filed: June 7, 2002
    Date of Patent: November 22, 2005
    Assignee: Mega Chips Corporation
    Inventor: Gen Sasaki
  • Patent number: 6961085
    Abstract: CCD data is compressed by compression means and stored in a raw image data buffer (step 10). Then, the compressed data is expanded by expansion means, so that pixel data thereof is sequentially output to an RPU (step 11). The RPU executes real-time image processing on the pixel data, so that the processed data is stored in a processed data buffer in units of frames. Then, a CPU reads an image from the processed data buffer at a proper timing and performs software processing such as high-efficiency coding through a temporary storage data buffer, for storing and preserving the processed data in a storage medium (step 12). Thus provided is an image processing circuit capable of reducing the scale of buffer areas in a memory for remarkably reducing the cost for the memory as well as power consumption.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: November 1, 2005
    Assignee: Mega Chips Corporation
    Inventor: Gen Sasaki
  • Patent number: 6944358
    Abstract: Image dividing means of an RPU divides raw image data into divided image data A1 having 2048 horizontal pixels and A2 having 1024 horizontal pixels. The divided image data A1 is continuously processed in single pixel processing means and multiple pixel processing means and thereafter transferred to and stored in a buffer. The divided image data A2 is processed in the single pixel processing means and thereafter transferred to and temporarily stored in another buffer. The multiple pixel processing means reads and processes divided image data A2a stored in this buffer and thereafter transfers and stores the same to and in still another buffer. Image combining means reads divided image data A1b and A2b stored in the buffers and combines the same with each other. Thus, an image processing time and a cost can be reduced even if raw image data having horizontal pixels in a number exceeding the capacity of a line memory is received.
    Type: Grant
    Filed: December 19, 2001
    Date of Patent: September 13, 2005
    Assignee: Mega Chips Corporation
    Inventors: Kazuya Morimoto, Takashi Matsutani, Gen Sasaki