Patents by Inventor Graham R. Wolstenholme

Graham R. Wolstenholme has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220384341
    Abstract: Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.
    Type: Application
    Filed: August 11, 2022
    Publication date: December 1, 2022
    Inventors: Paolo Tessariol, Graham R. Wolstenholme, Aaron Yip
  • Patent number: 11430734
    Abstract: Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: August 30, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Paolo Tessariol, Graham R. Wolstenholme, Aaron Yip
  • Publication number: 20220230960
    Abstract: Microelectronic devices include stadium structures within a stack structure and substantially symmetrically distributed between a first pillar structure and a second pillar structure, each of which vertically extends through the stack structure. The stack structure includes a vertically alternating sequence of insulative materials and conductive materials arranged in tiers. Each of the stadium structures includes staircase structures having steps including lateral ends of some of the tiers. The substantially symmetrical distribution of the stadium structures, and fill material adjacent such structures, may substantially balance material stresses to avoid or minimize bending of the adjacent pillars. Related methods and systems are also disclosed.
    Type: Application
    Filed: April 7, 2022
    Publication date: July 21, 2022
    Inventors: Lifang Xu, Jian Li, Graham R. Wolstenholme, Paolo Tessariol, George Matamis, Nancy M. Lomeli
  • Patent number: 11393716
    Abstract: Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: July 19, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Chang Wan Ha, Graham R. Wolstenholme, Deepak Thimmegowda
  • Patent number: 11302634
    Abstract: Microelectronic devices include stadium structures within a stack structure and substantially symmetrically distributed between a first pillar structure and a second pillar structure, each of which vertically extends through the stack structure. The stack structure includes a vertically alternating sequence of insulative materials and conductive materials arranged in tiers. Each of the stadium structures includes staircase structures having steps including lateral ends of some of the tiers. The substantially symmetrical distribution of the stadium structures, and fill material adjacent such structures, may substantially balance material stresses to avoid or minimize bending of the adjacent pillars. Related methods and systems are also disclosed.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: April 12, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Lifang Xu, Jian Li, Graham R. Wolstenholme, Paolo Tessariol, George Matamis, Nancy M. Lomeli
  • Publication number: 20210257298
    Abstract: Microelectronic devices include stadium structures within a stack structure and substantially symmetrically distributed between a first pillar structure and a second pillar structure, each of which vertically extends through the stack structure. The stack structure includes a vertically alternating sequence of insulative materials and conductive materials arranged in tiers. Each of the stadium structures includes staircase structures having steps including lateral ends of some of the tiers. The substantially symmetrical distribution of the stadium structures, and fill material adjacent such structures, may substantially balance material stresses to avoid or minimize bending of the adjacent pillars. Related methods and systems are also disclosed.
    Type: Application
    Filed: February 13, 2020
    Publication date: August 19, 2021
    Inventors: Lifang Xu, Jian Li, Graham R. Wolstenholme, Paolo Tessariol, George Matamis, Nancy M. Lomeli
  • Publication number: 20210151375
    Abstract: Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.
    Type: Application
    Filed: December 28, 2020
    Publication date: May 20, 2021
    Inventors: Paolo Tessariol, Graham R. Wolstenholme, Aaron Yip
  • Patent number: 10879175
    Abstract: Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: December 29, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Paolo Tessariol, Graham R. Wolstenholme, Aaron Yip
  • Publication number: 20200365452
    Abstract: Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.
    Type: Application
    Filed: July 31, 2020
    Publication date: November 19, 2020
    Inventors: Chang Wan Ha, Graham R. Wolstenholme, Deepak Thimmegowda
  • Patent number: 10748811
    Abstract: Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: August 18, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Chang Wan Ha, Graham R. Wolstenholme, Deepak Thimmegowda
  • Publication number: 20190259703
    Abstract: Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.
    Type: Application
    Filed: May 7, 2019
    Publication date: August 22, 2019
    Inventors: Paolo Tessariol, Graham R. Wolstenholme, Aaron Yip
  • Publication number: 20190237362
    Abstract: Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.
    Type: Application
    Filed: April 8, 2019
    Publication date: August 1, 2019
    Inventors: Chang Wan Ha, Graham R. Wolstenholme, Deepak Thimmegowda
  • Patent number: 10290581
    Abstract: Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: May 14, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Paolo Tessariol, Graham R. Wolstenholme, Aaron Yip
  • Patent number: 10269626
    Abstract: Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: April 23, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Chang Wan Ha, Graham R. Wolstenholme, Deepak Thimmegowda
  • Publication number: 20180204799
    Abstract: Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.
    Type: Application
    Filed: March 9, 2018
    Publication date: July 19, 2018
    Inventors: Paolo Tessariol, Graham R. Wolstenholme, Aaron Yip
  • Publication number: 20180130700
    Abstract: Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.
    Type: Application
    Filed: January 10, 2018
    Publication date: May 10, 2018
    Inventors: Chang Wan Ha, Graham R. Wolstenholme, Deepak Thimmegowda
  • Patent number: 9941209
    Abstract: Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: April 10, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Paolo Tessariol, Graham R. Wolstenholme, Aaron Yip
  • Patent number: 9870941
    Abstract: Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: January 16, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Chang Wan Ha, Graham R. Wolstenholme, Deepak Thimmegowda
  • Publication number: 20170263556
    Abstract: Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.
    Type: Application
    Filed: March 11, 2016
    Publication date: September 14, 2017
    Inventors: Paolo Tessariol, Graham R. Wolstenholme, Aaron Yip
  • Publication number: 20170076977
    Abstract: Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.
    Type: Application
    Filed: November 22, 2016
    Publication date: March 16, 2017
    Inventors: Chang Wan Ha, Graham R. Wolstenholme, Deepak Thimmegowda