Patents by Inventor Graham R. Wolstenholme
Graham R. Wolstenholme has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9508591Abstract: Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.Type: GrantFiled: July 13, 2015Date of Patent: November 29, 2016Assignee: Micron Technology, Inc.Inventors: Chang Wan Ha, Graham R. Wolstenholme, Deepak Thimmegowda
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Publication number: 20150318203Abstract: Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.Type: ApplicationFiled: July 13, 2015Publication date: November 5, 2015Inventors: Chang Wan Ha, Graham R. Wolstenholme, Deepak Thimmegowda
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Patent number: 9082772Abstract: Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.Type: GrantFiled: November 20, 2013Date of Patent: July 14, 2015Assignee: Micron Technology, Inc.Inventors: Chang Wan Ha, Graham R. Wolstenholme, Deepak Thimmegowda
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Publication number: 20140138840Abstract: Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.Type: ApplicationFiled: November 20, 2013Publication date: May 22, 2014Applicant: MICRON TECHNOLOGY, INC.Inventors: Chang Wan Ha, Graham R. Wolstenholme, Deepak Thimmegowda
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Publication number: 20140008806Abstract: Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.Type: ApplicationFiled: July 6, 2012Publication date: January 9, 2014Applicant: MICRON TECHNOLOGY, INC.Inventors: Chang Wan Ha, Graham R. Wolstenholme, Deepak Thimmegowda
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Patent number: 8609536Abstract: Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.Type: GrantFiled: July 6, 2012Date of Patent: December 17, 2013Assignee: Micron Technology, Inc.Inventors: Chang Wan Ha, Graham R. Wolstenholme, Deepak Thimmegowda
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Patent number: 8034716Abstract: Semiconductor structures and methods of making a vertical diode structure are provided. The vertical diode structure may have associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer may be formed over the interior surface of the diode opening and contacting the active region. The diode opening may initially be filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that may be heavily doped with a first type dopant and a bottom portion that may be lightly doped with a second type dopant. The top portion may be bounded by the bottom portion so as not to contact the titanium silicide layer. In one embodiment of the vertical diode structure, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.Type: GrantFiled: May 1, 2009Date of Patent: October 11, 2011Assignee: Micron Technology, Inc.Inventors: Fernando Gonzalez, Tyler A. Lowrey, Trung T. Doan, Raymond A. Turi, Graham R. Wolstenholme
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Publication number: 20090218656Abstract: Semiconductor structures and methods of making a vertical diode structure are provided. The vertical diode structure may have associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer may be formed over the interior surface of the diode opening and contacting the active region. The diode opening may initially be filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that may be heavily doped with a first type dopant and a bottom portion that may be lightly doped with a second type dopant. The top portion may be bounded by the bottom portion so as not to contact the titanium silicide layer. In one embodiment of the vertical diode structure, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.Type: ApplicationFiled: May 1, 2009Publication date: September 3, 2009Applicant: MICRON TECHNOLOGY, INC.Inventors: Fernando Gonzalez, Tyler A. Lowrey, Trung Tri Doan, Raymond A. Turi, Graham R. Wolstenholme
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Patent number: 7563666Abstract: Semiconductor structures and methods of making a vertical diode structure are provided. The vertical diode structure may have associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer may be formed over the interior surface of the diode opening and contacting the active region. The diode opening may initially be filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that may be heavily doped with a first type dopant and a bottom portion that may be lightly doped with a second type dopant. The top portion may be bounded by the bottom portion so as not to contact the titanium silicide layer. In one embodiment of the vertical diode structure, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.Type: GrantFiled: October 9, 2007Date of Patent: July 21, 2009Assignee: Micron Technology, Inc.Inventors: Fernando Gonzalez, Tyler A. Lowrey, Trung Tri Doan, Raymond A. Turi, Graham R. Wolstenholme
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Patent number: 7563679Abstract: A dielectric layer (e.g., an interpoly dielectric layer) is deposited over low and high voltage devices of a peripheral memory device. The dielectric behaves as an oxidation and wet oxide etch barrier. The dielectric prevents the devices from being stripped by a wet oxide etch that can result in the exposure of the silicon corners. The exposure of a silicon corner may increase thinning of a gate oxide at the field edge. This causes variability and unreliability in the device. The dielectric is not removed from a device until the device is ready for processing. That is, the dielectric remains on a device until the growing of a gate oxide on that device has begun. This reduces the exposure of the silicon corner. Hedges that result may be removed by exposing a trench in the field oxide at the hedge.Type: GrantFiled: July 18, 2007Date of Patent: July 21, 2009Assignee: Micron Technology, Inc.Inventors: Graham R. Wolstenholme, Mark A. Helm
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Patent number: 7279725Abstract: A method of making a vertical diode structure is provided, the vertical diode structure having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and contacts the active region. The diode opening is initially filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that is heavily doped with a first type dopant and a bottom portion that is lightly doped with a second type dopant. The top portion is bounded by the bottom portion so as not to contact the titanium silicide layer. For one embodiment of the vertical diode structure, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.Type: GrantFiled: August 24, 2005Date of Patent: October 9, 2007Assignee: Micron Technology, Inc.Inventors: Fernando Gonzalez, Tyler A. Lowrey, Trung Tri Doan, Raymond A. Turi, Graham R. Wolstenholme
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Patent number: 7262102Abstract: A dielectric layer (e.g., an interpoly dielectric layer) is deposited over low and high voltage devices of a peripheral memory device. The dielectric behaves as an oxidation and wet oxide etch barrier. The dielectric prevents the devices from being stripped by a wet oxide etch that can result in the exposure of the silicon corners. The exposure of a silicon corner may increase thinning of a gate oxide at the field edge. This causes variability and unreliability in the device. The dielectric is not removed from a device until the device is ready for processing. That is, the dielectric remains on a device until the growing of a gate oxide on that device has begun. This reduces the exposure of the silicon corner. Hedges that result may be removed by exposing a trench in the field oxide at the hedge.Type: GrantFiled: September 23, 2005Date of Patent: August 28, 2007Assignee: Micron Technology, Inc.Inventors: Graham R Wolstenholme, Mark A Helm
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Patent number: 7241662Abstract: A dielectric layer (e.g., an interpoly dielectric layer) is deposited over low and high voltage devices of a peripheral memory device. The dielectric behaves as an oxidation and wet oxide etch barrier. The dielectric prevents the devices from being stripped by a wet oxide etch that can result in the exposure of the silicon corners. The exposure of a silicon corner may increase thinning of a gate oxide at the field edge. This causes variability and unreliability in the device. The dielectric is not removed from a device until the device is ready for processing. That is, the dielectric remains on a device until the growing of a gate oxide on that device has begun. This reduces the exposure of the silicon corner. Hedges that result may be removed by exposing a trench in the field oxide at the hedge.Type: GrantFiled: June 24, 2002Date of Patent: July 10, 2007Assignee: Micron Technology, Inc.Inventors: Graham R Wolstenholme, Mark A Helm
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Patent number: 7170103Abstract: A method of making a vertical diode is provided, the vertical diode having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and contacts the active region. The diode opening is initially filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that is heavily doped with a first type dopant and a bottom portion that is lightly doped with a second type dopant. The top portion is bounded by the bottom portion so as not to contact the titanium silicide layer. For one embodiment of the vertical diode, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.Type: GrantFiled: August 24, 2005Date of Patent: January 30, 2007Assignee: Micron Technology, Inc.Inventors: Fernando Gonzalez, Tyler A. Lowrey, Trung Tri Doan, Raymond A. Turi, Graham R. Wolstenholme
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Patent number: 7166875Abstract: A method of making a vertical diode is provided, the vertical dioxide having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and contacts the active region. The diode opening is initially filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that is heavily doped with a first type dopant and a bottom portion that is lightly doped with a second type dopant. The top portion is bounded by the bottom portion so as not to contact the titanium silicide layer. For one embodiment of the vertical diode, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.Type: GrantFiled: March 19, 2004Date of Patent: January 23, 2007Assignee: Micron Technology, Inc.Inventors: Fernando Gonzalez, Tyler A. Lowrey, Trung Tri Doan, Raymond A. Turi, Graham R. Wolstenholme
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Publication number: 20040224464Abstract: A method of making a vertical diode is provided, the vertical dioxide having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and contacts the active region. The diode opening is initially filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that is heavily doped with a first type dopant and a bottom portion that is lightly doped with a second type dopant. The top portion is bounded by the bottom portion so as not to contact the titanium silicide layer. For one embodiment of the vertical diode, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.Type: ApplicationFiled: March 19, 2004Publication date: November 11, 2004Applicant: Micron Technology, Inc.Inventors: Fernando Gonzalez, Tyler A. Lowrey, Trung Tri Doan, Raymond A. Turi, Graham R. Wolstenholme
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Patent number: 6787401Abstract: A method of making a vertical diode is provided, the vertical dioxide having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and contacts the active region. The diode opening is initially filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that is heavily doped with a first type dopant and a bottom portion that is lightly doped with a second type dopant. The top portion is bounded by the bottom portion so as not to contact the titanium silicide layer. For one embodiment of the vertical diode, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.Type: GrantFiled: March 22, 2002Date of Patent: September 7, 2004Assignee: Micron Technology, Inc.Inventors: Fernando Gonzalez, Tyler A. Lowrey, Trung Tri Doan, Raymond A. Turi, Graham R. Wolstenholme
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Patent number: 6784046Abstract: A method of making a vertical diode is provided, the vertical dioxide having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and contacts the active region. The diode opening is initially filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that is heavily doped with a first type dopant and a bottom portion that is lightly doped with a second type dopant. The top portion is bounded by the bottom portion so as not to contact the titanium silicide layer. For one embodiment of the vertical diode, a programable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.Type: GrantFiled: March 22, 2002Date of Patent: August 31, 2004Assignee: Micron Techology, Inc.Inventors: Fernando Gonzalez, Tyler A. Lowrey, Trung Tri Doan, Raymond A. Turi, Graham R. Wolstenholme
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Patent number: 6750091Abstract: A method of making a vertical diode is provided, the vertical dioxide having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and contacts the active region. The diode opening is initially filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that is heavily doped with a first type dopant and a bottom portion that is lightly doped with a second type dopant. The top portion is bounded by the bottom portion so as not to contact the titanium silicide layer. For one embodiment of the vertical diode, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.Type: GrantFiled: February 16, 2000Date of Patent: June 15, 2004Assignee: Micron TechnologyInventors: Fernando Gonzalez, Tyler A. Lowrey, Trung Tri Doan, Raymond A. Turi, Graham R. Wolstenholme
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Patent number: 6740552Abstract: A method of making a vertical diode is provided, the vertical dioxide having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and contacts the active region. The diode opening is initially filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that is heavily doped with a first type dopant and a bottom portion that is lightly doped with a second type dopant. The top portion is bounded by the bottom portion so as not to contact the titanium silicide layer. For one embodiment of the vertical diode, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.Type: GrantFiled: March 22, 2002Date of Patent: May 25, 2004Assignee: Micron Technology, Inc.Inventors: Fernando Gonzalez, Tyler A. Lowrey, Trung Tri Doan, Raymond A. Turi, Graham R. Wolstenholme