Abstract: A method of fabricating an electrically-programmable read-only-memory (EPROM) or a flash memory array structure that controls oxide thinning to prevent shorts in the array and trenching of the bit lines is provided. The method includes the following steps. First, in accordance with conventional processing techniques, layers of gate oxide, polyl, ONO, poly cap, and nitride are sequentially deposited on the substrate. Next, in accordance with the present invention, a layer of thin poly is deposited on the layer of nitride. The thin poly/nitride/poly cap/ONO/polyl layers are then etched to define thin poly/nitride/poly cap/ONO/polyl parallel strips. Edge oxide is then formed on the thin poly/nitride/poly cap/ONO/polyl strips. Following this, a layer of spacer oxide is formed over the layer of edge oxide. An anisotropic etch back of the layers of spacer oxide and edge oxide is then performed until the thin poly layer and the substrate are exposed.

Abstract: An electrically programmable nonvolatile semiconductor memory which includes an array of programmable transistor cells, such as EPROM cells, which avoids the use of field oxide islands to provide electrical isolation. The cells are arranged in X number of rows and Y number of columns with the cells in at least two of the rows being designated as select cells and the remaining cells being designated as memory cells. Control circuitry is provided for causing the select cells to supplying programming voltages to selected ones of the memory cells. Alternate ones of the select cells are initially programmed to a high threshold (inactive) state so as to provide electrical isolation for adjacent select cells which remain in the low threshold (active) state.