Patents by Inventor Graham R. Wolstenholme
Graham R. Wolstenholme has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6692328Abstract: A toy, such as a toy pager or a toy telephone, generates an attention signal and plays a recorded message to the user. The attention signal is generated in a seemingly random fashion to simulate the operation of a real pager or telephone.Type: GrantFiled: March 25, 1997Date of Patent: February 17, 2004Assignee: Micron Technology, Inc.Inventors: Alan R. Reinberg, Graham R. Wolstenholme
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Publication number: 20030235964Abstract: A dielectric layer (e.g., an interpoly dielectric layer) is deposited over low and high voltage devices of a peripheral memory device. The dielectric behaves as an oxidation and wet oxide etch barrier. The dielectric prevents the devices from being stripped by a wet oxide etch that can result in the exposure of the silicon corners. The exposure of a silicon corner may increase thinning of a gate oxide at the field edge. This causes variability and unreliability in the device. The dielectric is not removed from a device until the device is ready for processing. That is, the dielectric remains on a device until the growing of a gate oxide on that device has begun. This reduces the exposure of the silicon corner. Hedges that result may be removed by exposing a trench in the field oxide at the hedge.Type: ApplicationFiled: June 24, 2002Publication date: December 25, 2003Applicant: Micron Technology, Inc.Inventors: Graham R. Wolstenholme, Mark A. Helm
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Patent number: 6653195Abstract: A vertically oriented diode for use in delivering current to a multi-state memory element in a memory cell. A vertical diode may be disposed in a diode container extending downwardly from a top of a silicon or oxide layer, and may be formed of a combination of silicon and/or metal layers disposed proximate to inner surfaces of a diode container. A multi-state memory element may be formed of a multi-state material, such as a chalcogenide, above a diode to complete a memory cell.Type: GrantFiled: May 12, 2000Date of Patent: November 25, 2003Assignee: Micron Technology, Inc.Inventors: Fernando Gonzalez, Raymond A. Turi, Graham R. Wolstenholme, Charles L. Ingalls
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Patent number: 6429449Abstract: A vertically oriented diode for use in delivering current to a multi-state memory element in a memory cell. A vertical diode may be disposed in a diode container extending downwardly from a top of a silicon or oxide layer, and may be formed of a combination of silicon and/or metal layers disposed proximate to inner surfaces of a diode container. A multi-state memory element may be formed of a multi-state material, such as a chalcogenide, above a diode to complete a memory cell.Type: GrantFiled: May 12, 2000Date of Patent: August 6, 2002Assignee: Micron Technology, Inc.Inventors: Fernando Gonzalez, Raymond A. Turi, Graham R. Wolstenholme, Charles L. Ingalls
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Publication number: 20020102788Abstract: A method of making a vertical diode is provided, the vertical dioxide having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and contacts the active region. The diode opening is initially filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that is heavily doped with a first type dopant and a bottom portion that is lightly doped with a second type dopant. The top portion is bounded by the bottom portion so as not to contact the titanium silicide layer. For one embodiment of the vertical diode, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.Type: ApplicationFiled: March 22, 2002Publication date: August 1, 2002Inventors: Fernando Gonzalez, Tyler A. Lowrey, Trung Tri Doan, Raymond A. Turi, Graham R. Wolstenholme
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Publication number: 20020102839Abstract: A method of making a vertical diode is provided, the vertical dioxide having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and contacts the active region. The diode opening is initially filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that is heavily doped with a first type dopant and a bottom portion that is lightly doped with a second type dopant. The top portion is bounded by the bottom portion so as not to contact the titanium silicide layer. For one embodiment of the vertical diode, a programable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.Type: ApplicationFiled: March 22, 2002Publication date: August 1, 2002Inventors: Fernando Gonzalez, Tyler A. Lowrey, Trung Tri Doan, Raymond A. Turi, Graham R. Wolstenholme
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Publication number: 20020098716Abstract: A method of making a vertical diode is provided, the vertical dioxide having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and contacts the active region. The diode opening is initially filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that is heavily doped with a first type dopant and a bottom portion that is lightly doped with a second type dopant. The top portion is bounded by the bottom portion so as not to contact the titanium silicide layer. For one embodiment of the vertical diode, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.Type: ApplicationFiled: March 22, 2002Publication date: July 25, 2002Inventors: Fernando Gonzalez, Tyler A. Lowrey, Trung Tri Doan, Raymond A. Turi, Graham R. Wolstenholme
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Patent number: 6236059Abstract: A memory cell incorporating a chalcogenide element and a method of making same is disclosed. In the method, a doped silicon substrate is provided with two or more polysilicon plugs to form an array of diode memory cells. A layer of silicon nitride is disposed over the plugs. Using a poly-spacer process, small pores are formed in the silicon nitride to expose a portion of the polysilicon plugs. A chalcogenide material is disposed in the pores by depositing a layer of chalcogenide material on the silicon nitride layer and planarizing the chalcogenide layer to the silicon nitride layer using CMP. A layer of TiN is next deposited over the plugs, followed by a metallization layer. The TiN and metallization layers are then masked and etched to define memory cell areas.Type: GrantFiled: April 30, 1997Date of Patent: May 22, 2001Assignee: Micron Technology, Inc.Inventors: Graham R. Wolstenholme, Fernando Gonzalez, Russell C. Zahorik
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Patent number: 6194746Abstract: A vertical diode is provided having a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and contacts the active region. The diode opening is initially filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that is heavily doped with a first type dopant and a bottom portion that is lightly doped with a second type dopant. The top portion is bounded by the bottom portion so as not to contact the titanium silicide layer. For one embodiment of the vertical diode, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.Type: GrantFiled: September 9, 1998Date of Patent: February 27, 2001Assignee: Micron Technology, Inc.Inventors: Fernando Gonzalez, Tyler A. Lowrey, Trung Tri Doan, Raymond A. Turi, Graham R. Wolstenholme
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Patent number: 6153890Abstract: A memory cell incorporating a chalcogenide element and a method of making same is disclosed. In the method, a doped silicon substrate is provided with two or more polysilicon plugs to form an array of diode memory cells. A layer of silicon nitride is disposed over the plugs. Using a poly-spacer process, small pores are formed in the silicon nitride to expose a portion of the polysilicon plugs. A chalcogenide material is disposed in the pores by depositing a layer of chalcogenide material on the silicon nitride layer and planarizing the chalcogenide layer to the silicon nitride layer using CMP. A layer of TiN is next deposited over the plugs, followed by a metallization layer. The TiN and metallization layers are then masked and etched to define memory cell areas.Type: GrantFiled: August 13, 1999Date of Patent: November 28, 2000Assignee: Micron Technology, Inc.Inventors: Graham R. Wolstenholme, Fernando Gonzalez, Russell C. Zahorik
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Patent number: 6118135Abstract: A vertically oriented diode for use in delivering current to a multi-state memory element in a memory cell. A vertical diode may be disposed in a diode container extending downwardly from a top of a silicon or oxide layer, and may be formed of a combination of silicon and/or metal layers disposed proximate to inner surfaces of a diode container. A multi-state memory element may be formed of a multi-state material, such as a chalcogenide, above a diode to complete a memory cell.Type: GrantFiled: July 6, 1998Date of Patent: September 12, 2000Assignee: Micron Technology, Inc.Inventors: Fernando Gonzalez, Raymond A. Turi, Graham R. Wolstenholme, Charles L. Ingalls
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Patent number: 6111264Abstract: A method for fabricating an ultra-small pore or contact for use in chalcogenide memory cells specifically and in semiconductor devices generally in which disposable spacers are utilized to fabricate ultra-small pores or contacts. The pores thus defined have minimum lateral dimensions ranging from approximately 500 to 4000 Angstroms. The pores thus defined may then be used to fabricate a chalcogenide memory cell or other semiconductor devices.Type: GrantFiled: November 13, 1997Date of Patent: August 29, 2000Assignee: Micron Technology, Inc.Inventors: Graham R. Wolstenholme, Steven T. Harshfield, Raymond A. Turi, Fernando Gonzalez, Guy T. Blalock, Donwon Park
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Patent number: 5998244Abstract: A memory cell incorporating a chalcogenide element and a method of making same is disclosed. In the method, a doped silicon substrate is provided with two or more polysilicon plugs to form an array of diode memory cells. A layer of silicon nitride is disposed over the plugs. Using a poly-spacer process, small pores are formed in the silicon nitride to expose a portion of the polysilicon plugs. A chalcogenide material is disposed in the pores by depositing a layer of chalcogenide material on the silicon nitride layer and planarizing the chalcogenide layer to the silicon nitride layer using CMP. A layer of TiN is next deposited over the plugs, followed by a metallization layer. The TiN and metallization layers are then masked and etched to define memory cell areas.Type: GrantFiled: August 22, 1996Date of Patent: December 7, 1999Assignee: Micron Technology, Inc.Inventors: Graham R. Wolstenholme, Fernando Gonzalez, Russell C. Zahorik
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Patent number: 5985698Abstract: A vertically oriented diode for use in delivering current to a multi-state memory element in a memory cell. A vertical diode may be disposed in a diode container extending downwardly from a top of a silicon or oxide layer, and may be formed of a combination of silicon and/or metal layers disposed proximate to inner surfaces of a diode container. A multi-state memory element may be formed of a multi-state material, such as a chalcogenide, above a diode to complete a memory cell.Type: GrantFiled: April 30, 1997Date of Patent: November 16, 1999Assignee: Micron Technology, Inc.Inventors: Fernando Gonzalez, Raymond A. Turi, Graham R. Wolstenholme, Charles L. Ingalls
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Patent number: 5970336Abstract: A memory cell incorporating a chalcogenide element and a method of making same is disclosed. In the method, a doped silicon substrate is provided with two or more polysilicon plugs to form an array of diode memory cells. A layer of silicon nitride is disposed over the plugs. Using a poly-spacer process, small pores are formed in the silicon nitride to expose a portion of the polysilicon plugs. A chalcogenide material is disposed in the pores by depositing a layer of chalcogenide material on the silicon nitride layer and planarizing the chalcogenide layer to the silicon nitride layer using CMP. A layer of TiN is next deposited over the plugs, followed by a metallization layer. The TiN and metallization layers are then masked and etched to define memory cell areas.Type: GrantFiled: October 30, 1997Date of Patent: October 19, 1999Assignee: Micron Technology, Inc.Inventors: Graham R. Wolstenholme, Fernando Gonzalez, Russell C. Zahorik
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Patent number: 5854102Abstract: A vertical diode is provided having a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and contacts the active region. The diode opening is initially filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that is heavily doped with a first type dopant and a bottom portion that is lightly doped with a second type dopant. The top portion is bounded by the bottom portion so as not to contact the titanium silicide layer. For one embodiment of the vertical diode, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.Type: GrantFiled: September 5, 1997Date of Patent: December 29, 1998Assignee: Micron Technology, Inc.Inventors: Fernando Gonzalez, Tyler A. Lowrey, Trung Tri Doan, Raymond A. Turi, Graham R. Wolstenholme
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Patent number: 5831276Abstract: A vertically oriented diode for use in delivering current to a multi-state memory element in a memory cell. A vertical diode may be disposed in a diode container extending downwardly from a top of a silicon or oxide layer, and may be formed of a combination of silicon and/or metal layers disposed proximate to inner surfaces of a diode container. A multi-state memory element may be formed of a multi-state material, such as a chalcogenide, above a diode to complete a memory cell.Type: GrantFiled: July 22, 1996Date of Patent: November 3, 1998Assignee: Micron Technology, Inc.Inventors: Fernando Gonzalez, Raymond A. Turi, Graham R. Wolstenholme, Charles L. Ingalls
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Patent number: 5814527Abstract: A method for fabricating an ultra-small pore or contact for use in chalcogenide memory cells specifically and in semiconductor devices generally in which disposable spacers are utilized to fabricate ultra-small pores or contacts. The pores thus defined have minimum lateral dimensions ranging from approximately 500 to 4000 Angstroms. The pores thus defined may then be used to fabricate a chalcogenide memory cell or other semiconductor devices.Type: GrantFiled: July 22, 1996Date of Patent: September 29, 1998Assignee: Micron Technology, Inc.Inventors: Graham R. Wolstenholme, Steven T. Harshfield, Raymond A. Turi, Fernando Gonzalez, Guy T. Blalock, Donwon Park
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Patent number: 5751012Abstract: There is described a memory cell having a vertically oriented polysilicon pillar diode for use in delivering large current flow through a variable resistance material memory element. The pillar diode comprises a plurality of polysilicon layers disposed in a vertical stack between a wordline and digitline. The memory element is disposed in series with the diode, also between the wordline and the digitline. The diode is capable of delivering the large current flow required to program the memory element without also requiring the surface space on the upper surface of the memory matrix normally associated with such powerful diodes. The invention allows memory cells to be disposed every 0.7 microns or less across the face of a memory matrix. Further, the memory cell is easily fabricated using standard processing techniques. The unique layout of the inventive memory cell allows fabrication with as few as three mask steps or less.Type: GrantFiled: June 7, 1995Date of Patent: May 12, 1998Assignee: Micron Technology, Inc.Inventors: Graham R. Wolstenholme, Philip J. Ireland
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Patent number: 5496754Abstract: The bit lines in an alternate-metal, virtual-ground (AMG) electrically programmable read-only-memory (EPROM), are formed by utilizing a plurality of field oxide regions and a plurality of pairs of dielectric/floating gate strips, which have the ends of each pair of strips connected together over a field oxide region, as an implant mask. By connecting together the ends of each pair of dielectric/floating gate strips, the width of the strips at the edges of the field oxide regions will remain constant. As a result, the isolation between adjacent bit lines, which is defined by the width of the strips, will also remain constant.Type: GrantFiled: March 15, 1994Date of Patent: March 5, 1996Assignee: National Semiconductor CorporationInventors: Albert M. Bergemont, Graham R. Wolstenholme