Abstract: A method for controlling an amount of power consumed by an integrated circuit. The method includes decoding a plurality of information units by performing a number of decoding iterations on each of the plurality of information units, and generating a moving average of decoding iterations performed when decoding a selected number of information units of the plurality of information units. The method further includes adjusting the number of decoding iterations based on (i) the moving average of decoding iterations performed in decoding the selected number of information units of the plurality of information units and (ii) the amount of power consumed by the integrated circuit.

Abstract: Systems and methods are provided for using a product code having a first dimension and a second dimension to encode data, decode data, or both. An encoding method includes receiving a portion of user data to be written in the first dimension, and computing first parity symbols with respect to the first dimension for the portion of user data. Partial parity symbols with respect to the second dimension are computed for the portion of user data and are used to obtain second parity symbols for the portion of user data. A decoding method includes decoding a first codeword in the first dimension. When the decoding the first codeword in the first dimension is successful, a target syndrome of a second codeword in the second dimension is computed based on a result of the decoding of the first codeword, wherein the first codeword partially overlaps with the second codeword.

Abstract: A controller for a nonvolatile memory device includes a transfer control module and a decoder module. The transfer control module is configured to request a read of data from a flash memory module. The data to be read includes data corresponding to a first codeword. The transfer control module is configured to receive hard decisions corresponding to the first codeword from the flash memory module. The transfer control module is configured to receive soft information corresponding to the first codeword from the flash memory module. Both the hard decisions corresponding to the first codeword and the soft information corresponding to the first codeword are received without receiving any intervening hard decisions or soft information corresponding to another codeword. The decoder module is configured to decode the first codeword using the hard decisions and the soft information corresponding to the first codeword.

Abstract: A method for writing data onto a medium on which data are stored in tracks includes encoding the data into at least one codeword, and writing a respective portion of each of the at least one codeword onto respective different tracks on the medium. The writing may include writing a respective portion of each of the at least one codeword onto respective different adjacent tracks on the medium. Another method for reading data includes positioning a plurality of read heads to read codewords that have been written across multiple tracks of a medium. Each read head in the plurality of read heads reads a different portion of the first group of the multiple tracks, and where each different portion of the multiple tracks overlaps at least one other different portion of the multiple tracks. Signals are detected from the plurality of read heads, and the detected signals are decoded.

Abstract: Systems and methods for improving the performance of iterative decoders on various channels with memory are disclosed. These systems and methods may reduce the frequency or number of situations in which the iterative decoder cannot produce decoded data that matches the data that was originally sent in a communications or data storage system. The iterative decoder includes a SISO channel detector and an ECC decoder and decodes the coded information according to at least one iterative decoding algorithm in regular decoding mode and/or at least one iterative decoding algorithm in error-recovery mode.

Abstract: Systems, methods, apparatus, and techniques are provided for producing an estimate of a digital sequence. A continuous-time signal is obtained. The continuous-time signal is sampled with an oversampling factor to produce a discrete-time signal corresponding to the continuous-time signal. A phase offset estimate of the continuous-time signal is produced based on the discrete-time signal. The discrete-time signal is interpolated based on the phase offset estimate to produce an interpolated discrete-time signal. The interpolated discrete-time signal is processed to produce an estimate of a digital sequence.

Abstract: System and methods are provided for signal processing. For example, an input signal is received at a finite impulse response filter circuit including a plurality of stages, where each stage of the plurality of stages is associated with a sample value of the input signal and a stage weight. An output signal is generated using the finite impulse response filter circuit, the output signal being equal to a weighted sum of the sample values of the input signal. An error signal is generated to indicate a difference between the output signal and a target. A constraint is applied to one or more of the stage weights. The stage weights are changed within the constraint to reduce a magnitude of the error signal.

Abstract: Systems and methods for error recovery are presented. Data is decoded with an iterative decoding scheme having a first set of parameters. In response to a determination that the iterative decoding scheme has failed, the data is re-read. While the data is being re-read, the iterative decoding scheme is reconfigured with a second set of parameters, and the data is decoded with the reconfigured iterative decoding scheme. In response to determination that the reconfigured iterative decoding scheme has failed, an error type associated with the data is determined. An error recovery scheme is selected from a plurality of error recovery schemes for the data based on the determined error type.

Abstract: Systems, methods, and other embodiments associated with LDPC decoder architectures are described. According to one embodiment, a method includes decoding codeword bits with a high throughput LDPC decoder and when the decoding of the codeword bits with the high throughput LDPC decoder is unsuccessful, decoding the codeword bits with a low throughput LDPC decoder.

Abstract: A system including an inter-track interference detection module and a position error signal generation module. The inter-track interference detection module determines a first inter-track interference value based on a first signal from a first sensor positioned over a first track of a rotating storage medium. The first inter-track interference value indicates energy contributed by tracks adjacent to the first track compared to energy contributed by the first track. The inter-track interference detection module determines a second inter-track interference value based on a second signal from a second sensor positioned over a second track of the rotating storage medium. The second inter-track interference value indicates energy contributed by tracks adjacent to the second track compared to energy contributed by the second track. The position error signal generation module generates a position error signal based on the first inter-track interference value and the second inter-track interference value.

Abstract: Systems and methods for detection of defects on a magnetic storage medium. The method comprises: (1) receiving incoming detected data generated by reading information recorded on a storage medium, (2) identifying the defects in the storage medium based on comparison between the incoming detected data and a data pattern wherein the data pattern is predetermined; and (3) storing location information indicative of locations of the defects on the storage medium.

Abstract: In nonbinary iterative decoding, a data recovery scheme corrects for corrupted or defective data by determining reliability metrics for blocks of decoded nonbinary data. Block or windowed detectors generate block reliability metrics for data blocks (rather than individual bits) of decoded data using soft information from the regular decoding mode or from new iterative decoding iterations performed during defect detection mode. A defect detection system triggers corrective decoding of selected data blocks based on the block reliability metrics, by for example, comparing the block reliability metrics to a threshold or by selecting an adjustable number of the least reliable data blocks.

Abstract: A cryptographic device includes first and second pipeline stages and a pipeline register. The first pipeline stage includes a first byte substitution module configured to (i) receive a first data block including multiple bytes, (ii) perform predetermined mathematical operations on each of the bytes of the first data block, and (iii) for each of the bytes of the first data block, output an intermediate value based on the predetermined mathematical operations. The pipeline register is configured to store the intermediate values. The second pipeline stage includes a second byte substitution module configured to (i) receive the stored intermediate values from the pipeline register, and (ii) generate an output data block, for each intermediate value of the stored intermediate values, by performing predetermined mathematical operations on the intermediate value to generate a corresponding replacement byte of the output data block.

Abstract: Systems and methods are provided for decoding data. A first decoder attempts to decode the data based on a hard decision input for a symbol. When the attempt to decode the data based on the hard decision input fails, a request is transmitted reliability information for the symbol. Receiving circuitry receives the reliability information for the symbol, and a second decoder decodes the data based on the reliability information.

Abstract: Systems and methods are provided for calibrating signals retrieved from a storage device using a first reader and a second reader. The systems and methods further include reading a first signal using the first reader and a second signal using the second reader. Control circuitry computes a calibration metric associated with the first reader and the second reader based on the combination of the first signal and the second signal. At least one of the first signal and the second signal is subsequently decoded based in part on the computed calibration metric.

Abstract: Methods and systems are disclosed herein for generating parity information for using information in a low-density parity check (LDPC) encoder. A quasi-cyclic LDPC generator matrix K can be generated based on the non-invertible parity-check matrix H. Parity information can be generated by the LDPC encoder based at least in part on the user information, the non-invertible parity check matrix H, and the quasi-cyclic LDPC generator matrix K.

Abstract: The present disclosure describes systems and techniques relating to storage devices, such as storage devices that employ Shingled Magnetic Recording (SMR). According to an aspect of the described systems and techniques, a device includes: circuitry configured to write stored data and parity data to discrete portions of a Shingled Magnetic Recording (SMR) track in a SMR storage device; and circuitry configured to recover stored data for one of the discrete portions of the SMR track using the parity data and the stored data read from remaining ones of the discrete portions of the SMR track.

Abstract: Systems, methods, and apparatus are provided for improving the iterative decoding performance of a decoder, for example, as used in a wireless communications receiver or in a data retrieval unit. A decoding technique may receive and process a set of channel samples using an iterative decoder. If the iterative decoder output indicates a decoding failure, noise samples may foe combined with the received channel samples to create biased channel samples. Noise sample may be generated using a pseudo-random noise generator and/or by using signals already present in the communications receiver or data retrieval unit. The biased channel samples may be provided to the iterative decoder and the iterative decoder may re-run using the biased channel samples.

Abstract: Systems and methods are provided for selecting precisions during iterative decoding with a low-density parity check (LDPC) decoder in order to maximize LDPC code's performance in the error floor region. The selection of the precision of the messages may be done in such a way as to avoid catastrophic errors and to minimize the number of near-codeword errors during the decoding process. Another system and method to avoid catastrophic errors in the layered (serial) LDPC decoder is provided. Lastly, a system and method that select precisions and provide circuitry that optimizes the exchange of information between a soft-input, soft-output (SISO) channel detector and an error correction code (ECC) decoder for channels with memory is provided.

Abstract: A storage drive includes a first memory that stores first text. A first processor generates a first instruction to decrypt the first text. A cryptographic module includes a second memory, a cryptographic device, a memory module, and a second processor. The second memory is inaccessible to the first processor and stores a cryptographic key. The cryptographic device accesses the second memory to obtain the cryptographic key and based on the first instruction, decrypts the first text. The memory module stores a status of execution of the first instruction by the cryptographic device. The second processor, prior to the cryptographic device decrypting the first text, forwards the first instruction to the cryptographic device and stores the status of execution of the first instruction in the memory module. The memory module is connected between the first and second processors and isolates the first processor from the second processor.