Abstract: In iterative decoding, a data recovery scheme corrects for corrupted or defective data by determining reliability metrics for blocks of decoded data. Block or windowed detectors generate block reliability metrics for data blocks (rather than individual bits) of decoded data using soft information from the regular decoding mode or from new iterative decoding iterations performed during error recovery mode. An error recovery system triggers corrective decoding of selected data blocks based on the block reliability metrics, by for example, comparing the block reliability metrics to a threshold or by selecting an adjustable number of the least reliable data blocks.

Abstract: Systems, methods, apparatus, and techniques are provided for decoding data. A plurality of codewords are received in a first order, the first order different from a second order in which the plurality of codewords was encoded, a CRC check is initiated in the first order on each of the plurality of codewords to produce a respective plurality of codeword-level CRC values, the plurality of codeword-level CRC values is combined to produce an overall CRC sequence, and it is determined if there is an error in the plurality of codewords based on the overall CRC sequence.

Abstract: A control module includes an encoder module, a detector module, a mapping module, and a difference module. The encoder module receives data, and based on the data, generates a first code word for drives. The drives are associated with a storage system. The detector module detects an addition of a second drive. The encoder module generates a second code word for the second drive. The mapping module: maps physical locations of the data in the drives to logical locations of the first code word; assigns a predetermined value to a logical location corresponding to an unused logical location; and based on the predetermined value, assigns the unused logical location to the second drive. The difference module generates a third code word based on each of the first and second code words. The encoder module, based on the first and third code words, generates a fourth code word for all drives.

Abstract: Systems and techniques relating to fault tolerant data storage in storage devices, such as storage devices that employ Shingled Magnetic Recording (SMR) and/or storage devices that employ solid state memory, include a method, in some implementations, including: receiving, at a storage controller, a data request for a storage device; reading, in response to the data request, data from discrete units of storage in the storage device, the data comprising stored data read from two or more of the discrete units of storage and parity data read from at least one of the discrete units of storage; detecting an error in the stored data from the reading; and recovering stored data for at least one of the discrete units of storage using the parity data and the stored data read from one or more remaining ones of the two or more of the discrete units of storage.

Abstract: Systems, methods, apparatus, and techniques are provided for producing encoded trellis coded modulation (TCM) data from user information. Encoding parameters are selected based on a target information rate. The encoding parameters include a first dimensionality value and a second dimensionality value. A first part of the user information is encoded based on the first dimensionality value to produce a first number of coded bits, and a second part of the user information is encoded based on the second dimensionality value to produce a second number of coded bits.

Abstract: Systems, methods, apparatus, and techniques are provided for producing an estimate of a digital sequence. A continuous-time signal is obtained. The continuous-time signal is sampled with an oversampling factor to produce a discrete-time signal corresponding to the continuous-time signal. A phase offset estimate of the continuous-time signal is produced based on the discrete-time signal. The discrete-time signal is interpolated based on the phase offset estimate to produce an interpolated discrete-time signal. The interpolated discrete-time signal is processed to produce an estimate of a digital sequence.

Abstract: An error correction system includes an iterative code that employs an interleaved component code and an embedded parity component code. In some embodiments, on the transmission side, input signals received at an input node are encoded based on the interleaved code, which encodes an interleaved version of the input data to produce a first set of codewords. At least a portion of the first set of codewords preferably is divided into a plurality of symbols which are encoded based on the embedded parity code to provide encoded data. Similarly, in some embodiments, on the receiving side, received data are detected to produce detected information and soft outputs. The detected information is decoded based on the embedded parity code to obtain decoded information. The decoded information preferably is used, together with other soft information, by an interleaved decoder to generate reliability metrics for biasing a subsequent decoding iteration.

Abstract: Systems, methods, and other embodiments associated with LDPC decoder architectures are described. According to one embodiment, an apparatus includes a super-parity-check matrix corresponding to at least a portion of a low density parity check (LDPC) code matrix. The super-parity-check-matrix is configured to operate with nx check node processing elements (NPEs) and ny bit NPEs. The super-parity-check matrix includes a plurality of parity check matrices. Each parity check matrix is configured to operate with x check NPEs and y bit NPEs. The numbers n, x, and y, are selected such that ny codeword bits are processed in the single time unit by a high throughput decoder and y codeword bits are processed in the single time unit by a low throughput decoder.

Abstract: In one or more embodiments, an integrated circuit includes a programmable memory, a key generation module and a module. The programmable memory is to maintain a first key portion. The key generation module is to generate a key using the first key portion from the programmable memory and a second key portion received via a memory interface. The module is to encrypt or decrypt data using the key.

Abstract: A method for reading a track of data may include positioning a read head at an initial position relative to the track of data and obtaining initial track signals, filtering the initial track signals, positioning the read head at an initial subsequent position relative to the track of data and obtaining initial subsequent track signals, and filtering the initial subsequent track signals. In an initial equalization, the filtered initial track signals and the filtered initial subsequent track signals are equalized to obtain equalized track signals. The read head is positioned at a further subsequent position relative to the track of data and further subsequent track signals are obtained The further subsequent track signals are filtered. In a subsequent equalization, previously obtained equalized track signals and the filtered further subsequent track signals are equalized. A storage device operating according to the method may have an equalizer in hardware or firmware.

Abstract: Systems and methods are provided for evaluating an asymmetry metric. A receiver receives a synchronization signal, a filtered signal, and a reference signal. A processor processes the synchronization signal and the reference signal to obtain a peak indicator signal, identifies a first set of values and a second set of values from the filtered signal based at least in part on the peak indicator signal, and evaluates an asymmetry metric from the first set of values and the second set of values.

Abstract: A read/write channel module including a sampling module configured to sample a read signal corresponding to data stored on a disk. A first preamble is encoded with a first timing recovery pattern on a first track of the disk. The first timing recovery pattern includes a first pattern that changes every x bits. A second preamble is encoded with a second timing recovery pattern on a second track of the disk adjacent to the first track. The second timing recovery pattern includes a second pattern that changes every y bits. A data processing module is configured to process the read signal to remove inter track interference from the read signal based on a difference between the first timing recovery pattern and the second timing recovery pattern.

Abstract: Systems and techniques relating to control of magnetic recording devices are described. Such devices can contain a recording medium including magnetic data positions, servo sync marks (SSMs), and phase tracking fields (PTFs) arranged between first and second SSMs. A described technique includes producing, based on a read head's waveform from the recoding medium, a servo detect pulse indicating a SSM detection; producing, based on the waveform, a servo detect pulse that indicates a SSM detection; producing, responsive to the servo detect pulse, calibration pulses, each of the calibration pulses corresponding to a read head's passage over one of the PTFs; and controlling, responsive to the calibration pulses, adjustments of a phase of a write clock signal to align the write clock signal with at least a portion of the data positions, the adjustments being based on groups of samples of the waveform that respectively correspond to the PTFs.

Abstract: A read module reads memory cells along a first word line by applying a plurality of threshold voltages to the first word line; generates first information about a first memory cell located along the first word line and a first bit line indicating a location of a threshold voltage distribution of the first memory cell relative to the plurality of threshold voltages; reads a second memory cell located along the first word line, a second word line near the first word line, or a second bit line near the first bit line; and generates second information about the second memory cell indicating a state of the second memory cell causing interference to the first memory cell. A compensation module compensates for the interference by assigning one or more of a log-likelihood ratio and a hard decision to the first memory cells based on the first information and the second information.

Abstract: An apparatus includes a circuit configured to at least one of (i) encode first data to produce encoded data or (ii) decode second data to produce decoded data. The circuit is configured to operate according to a predetermined matrix. The predetermined matrix is represented by a two-dimensional grid of elements. Each element of the predetermined matrix labeled with a hyphen corresponds to a zero matrix. Each element of the predetermined matrix labeled with a number corresponds to a respective cyclic-permutation matrix.

Abstract: Embodiments provide a method comprising estimating a first set of log-likelihood ratio (LLR) values for a plurality of memory cells of a memory; based on the first set of LLR values, performing a first error correcting code (ECC) decoding operation; in response to determining a failure of the first ECC decoding operation, generating, by adjusting the first set of LLR values, a second set of LLR values for the plurality of memory cells; and based on the second set of LLR values, performing a second ECC decoding operation.

Abstract: This disclosure relates generally to low power data decoding, and more particularly to low power iterative decoders for data encoded with a low-density parity check (LDPC) encoder. Systems and methods are disclosed in which a low-power syndrome check may be performed in the first iteration or part of the first iteration during the process of decoding a LDPC code in an LDPC decoder. Systems and methods are also disclosed in which a control over the precision of messages sent or received and/or a change in the scaling of these messages may be implemented in the LDPC decoder. The low-power techniques described herein may reduce power consumption without a substantial decrease in performance of the applications that make use of LDPC codes or the devices that make use of low-power LDPC decoders.

Abstract: A hardware architecture for encryption and decryption device can improve the encryption and decryption data rate by using parallel processing, and pipeline operation, and save footprint by sharing hardware components. The hardware architecture can also be associated with a memory to protect the information stored at the memory. The encryption device can include a tweaking value manager to generate an array of tweaking values corresponding to the array of data blocks based on a tweaking encryption key, a first encryption unit to encrypt a first portion of the array of data blocks into a first portion of encrypted data blocks based on corresponding tweaking values and a data encryption key, a second encryption unit to encrypt a second portion of the array of data blocks, and a data block combiner to combine the first portion of encrypted data blocks and the second portion of encrypted data blocks.

Abstract: A hard disk drive circuit includes first and second inter-track interference detection modules. The first inter-track interference detection module is configured to generate a first measured inter-track interference value based on a first read signal from a first read sensor positioned over a magnetic medium. The second inter-track interference detection module is configured to generate a second measured inter-track interference value based on a second read signal from a second read sensor positioned over the magnetic medium. A position error signal generation module is configured to generate a position error signal based on the first measured inter-track interference value and the second measured inter-track interference value. An arm control module is configured to control rotation of an arm in response to the position error signal. The first read sensor and the second read sensor are located at a distal end of the arm.

Abstract: Determining the radial position of a first read head of a storage device includes reading servo data from a storage media platter surface using the first read head, deriving from that servo data a first positron error signal representing a first estimate of the radial position of the first read head, reading the servo data from the storage media platter surface using a different read head, deriving from that servo data a second position error signal representing an estimate of the radial position of the different read head, and combining the first estimate of the radial position of the first read head and the estimate of the radial position of the different read head to obtain a revised estimate of the radial position of the first read head. The combining could include taking account of a known positional offset between the first read head and the different read head.