Abstract: Systems and techniques relating to storage devices, such as storage devices that employ Shingled Magnetic Recording (SMR), can include a device, which includes: circuitry configured to write stored data and parity data to discrete portions of a Shingled Magnetic Recording (SMR) track in a SMR storage device; and circuitry configured to recover stored data for one of the discrete portions of the SMR track using the parity data and the stored data read from remaining ones of the discrete portions of the SMR track.

Abstract: Systems and methods for power efficient iterative equalization on a channel are provided. An iterative decoder decodes received data from a channel detector using a decoding process. The decoder computes a decision metric based on the decoded data and adjusts the number of iterations of the decoding process based on the decision metric. The adjustment occurs prior to a reliability criterion for the decoded data being satisfied. The decoder may pass control back to the channel detector if the adjusted number of iterations has occurred or if the reliability criterion is satisfied. Adjusting the number of iterations of the decoding process may include increasing the number of iterations from a predetermined number of iterations. The decision metric may be based on syndrome weight or hard decisions. The decision metric may be chosen to reduce average power consumption of the detector, the decoder, or circuitry including the detector and the decoder.

Abstract: The present disclosure includes systems and techniques relating to synchronization for writing to a recording medium. According to an aspect, an apparatus includes: circuitry configured to measure a timing difference based on a servo detect pulse and a write pulse, wherein the servo detect pulse comes from a detection of servo data from a recording medium including pre-defined data positions, and wherein the write pulse comes from a write clock signal used with the recording medium; and circuitry configured to control an adjustment to a phase of the write clock signal based on the timing difference to align the write clock signal with at least a portion of the pre-defined data positions.

Abstract: Systems and methods are provided for decoding data using hard decisions and soft information. In particular, the systems and methods described herein are directed to decoders having variable nodes and check nodes, each with multiple states. The systems and methods include receiving, at a decoder during a first iteration, values for each of a plurality of variable nodes, and determining, during a second iteration, one or more indications for each of a plurality of check nodes based on the one or more values of the variable nodes received during the first iteration. The methods further include updating, at the decoder during the second iteration, the values for each of the variable nodes based on the values of the respective variable node received during the first iteration, and the indications for each of the plurality connected check nodes during the first iteration.

Abstract: Systems and methods are provided for improved designs and performance for iterative decoder systems. In some embodiments, the iterative decoder may be decoupled from FIR samples through an FIR RAM, thus resulting in a less complex design and shorter processing times. In some embodiments, an intermediate memory may be used when passing information between the SOVA and LDPC of the iterative decoder. In some embodiments, the SOVA-required information may be continuously serialized from information received from the LDPC during each LDPC iteration. In some embodiments, the 1/(1+D2) precoder of the HR RLL encoder may be split into two serial, 1/(1+D) precoders. One 1/(1+D) precoder may be pulled outside of the HR RLL encoder and used in conjunction with the iterative decoder. A 1/(1+D) precoder may be used with the iterative decoder while maintaining the RLL constraints imposed upon the encoded information by the HR RLL encoder.

Abstract: The present disclosure includes systems and techniques relating to implementing fault tolerant data storage in solid state memory. In some implementations, a method includes receiving a data request for a solid state memory; identifying a logical block grouping corresponding to the data request, wherein the logical block grouping indicates physical data storage blocks spanning at least two distinct memory units of the solid state memory; reading stored data and parity information from at least a portion of the physical data storage blocks spanning the at least two distinct memory units; and recovering data of at least one block of the logical block grouping based on the stored data and the parity information.

Abstract: Apparatus, methods, and other embodiments associated with group based read reference voltage management in flash memory are described. According to one embodiment, an apparatus includes a partition logic, a Vref memory, and a Vref logic. The partition logic is configured to assign respective cells in a flash memory device to respective groups of cells. The Vref memory is configured to store respective Vref values mapped to respective groups of cells. The read logic is configured to read a cell in the flash memory by determining a group to which the cell is assigned; determining a Vref mapped to the group; and using the Vref value to read the cell. In one embodiment, the apparatus includes an adaptation logic configured to selectively adapt respective Vref values mapped to the respective groups of cells.

Abstract: A system including a first filter module configured to receive an input signal including (i) a first shift in a DC level of the input signal and (ii) a second shift in the DC level of the input signal. The first shift has (i) a first magnitude and (ii) a first duration. The second shift has (i) a second magnitude and (ii) a second duration. The second magnitude is different than the first magnitude. The second duration is greater than the first duration. The first filter module is configured to pass the first shift. The second filter module is configured to detect one or more of (i) the first shift and (ii) the second shift, and in response to detecting one or more of (i) the first shift and (ii) the second shift, filter one or more of (i) the first shift and (ii) the second shift.

Abstract: Techniques are provided for performing bit-locked operations on media. A first control signal is received from a first source, and a second control signal is generated at a second source in response to receiving the first control signal. The media is accessed according to the second control signal. One or more synchronization markers are located during the accessing of the media, and bit-level synchronization between the second source and the media is achieved based, at least partially, on the one or more synchronization markers. A control operation is performed on the media with bit-level synchrony between the second source and the media.

Abstract: Systems and methods are provided for decoding data using hard decisions and erasures. Circuitry receives data from each of a plurality of variable nodes which correspond to bits of data being decoded. Each variable node stores one of at least three values. The circuitry determines processes the values received from the plurality of variable nodes according to a set of processing rules. The processing rules are used to determine a condition related to the values stored by the plurality of variable nodes. The circuitry stores an indication of the stored condition at a check node.

Abstract: Systems and methods are provided for calibrating signals retrieved from a storage device using a first reader and a second reader. The systems and methods further include reading a first signal using the first reader and a second signal using the second reader. Control circuitry computes a calibration metric associated with the first reader and the second reader based on the combination of the first signal and the second signal. At least one of the first signal and the second signal is subsequently decoded based in part on the computed calibration metric.

Abstract: Methods and apparatuses are provided for decoding a codeword using an iterative decoder. The iterative decoder, in a first decoding mode, performs a number of channel iterations on the codeword, determines a first syndrome weight after a first time period, and determines a second syndrome weight after a second time period. Each channel iteration includes an iteration of the channel detector and at least one iteration of the inner iterative decoder. The iterative decoder, in a second decoding mode, determines a true syndrome of the codeword, and processes the codeword based on the true syndrome of the codeword. The codeword is processed using the second decoding mode in response to determining that the first and second determined syndrome weights are less than a syndrome weight threshold.

Abstract: Systems and methods for storing data on a storage device are disclosed. Data for storage to one of a plurality of tracks of the storage device is received. Each of the plurality of tracks includes a plurality of sectors. The received data is encoded using a track level code. The track level code encodes multiple of the plurality of sectors of the one of the plurality of tracks. The encoded data is stored to the one of the plurality of tracks of the storage device.

Abstract: Systems and methods for decoding a received codeword are provided. The received codeword is decoded based on a parity code to produce a plurality of checks. A first unsatisfied check is selected from the plurality of checks, and a first set of symbol positions in the received codeword that are connected to the first unsatisfied check is identified. A second set of symbol positions in the received codeword that are not connected to the first unsatisfied check is identified. The received codeword is modified by setting the first set of symbol positions to first predetermined values and by setting the second set of symbol positions to second predetermined values. The modified received codeword is decoded based on the parity code.

Abstract: In one embodiment a data decoding apparatus includes first and second decoding blocks configured to decode codeword bits in a first mode determined by a first probability of non-standard errors and a second mode determined by a second probability of non-standard errors. The apparatus also includes a mode modification logic configured to cause at least one of the first and second decoding blocks to operate in the second mode when the first and second decoding blocks fail to decode the codeword bits in the first mode. In another embodiment, a method includes decoding codeword bits in a first mode determined by a first probability of non-standard errors. When decoding the codeword bits in the first mode fails to decode the codeword bits, the codeword bits are decoded in a second mode determined by a second probability of non-standard errors.

Abstract: Methods, apparatuses, and systems for comparing threshold voltages of a plurality of flash memory cells to a plurality of reference voltages. A number of flash memory cells having threshold voltages that fall within each bin of a plurality of bins is determined. The plurality of bins each represent a plurality of threshold voltage ranges. A threshold voltage distribution of the plurality of flash memory cells is calculated based at least in part on the number of flash memory cells that fall into each of the bins.

Abstract: An integrated circuit including a decoding module, a moving average module, and an iteration control module. The decoding module is configured to decode a plurality of information units by performing a number of decoding iterations on each of the plurality of information units. The moving average module is configured to generate a moving average of decoding iterations performed when decoding a selected number of information units of the plurality of information units. The iteration control module is configured to adjust the number of decoding iterations based on (i) the moving average of decoding iterations performed in decoding the selected number of information units of the plurality of information units and (ii) an amount of power consumed by the integrated circuit.

Abstract: An apparatus includes, in at least one aspect, a memory interface configured to connect with a plurality of multi-level memory cells and a circuitry coupled with the memory interface. The plurality of multi-level memory cells include a first page and a second page. The first page is associated with bits of a first significance. The second page is associated with bits of a second significance. The circuitry is configured to map a first portion of an encoded data sector to the first page and map a second portion of the encoded data sector to the second page. The first portion excludes the second portion and the second portion excludes the first portion such that each of the first page and the second page contains different data from the encoded data sector.

Abstract: A method includes selecting a first memory cell located along a first bit line and a first word line of a memory array. The method further includes selecting a second memory cell located along (i) the first word line, (ii) a second word line that is adjacent to the first word line, or (iii) a second bit line that is adjacent to the first bit line. A location of the second memory cell is selected based on a predetermined sequence of programming the memory cells. The method further includes writing data in the first memory cell, subsequently writing data in the second memory cell, and reading the first memory cell and the second memory cell. The method further includes detecting one or more states of the second memory causing interference to the first memory cell.

Abstract: A transceiver includes a transmitter and a receiver. The transmitter includes an ECC encoder and a data frame generator. The ECC encoder is configured to generate an ECC parity from user data and at least one bit from a syncmark. The data frame generator is configured to generate a data frame for transmission from the syncmark, the user data, and the ECC parity. The receiver includes a detector, an inverter, and a decoder. The detector is configured to detect a received syncmark in a received data frame. The received data frame includes the received syncmark, received user data, and received ECC parity. The inverter is configured to selectively invert a sequence. The sequence includes the received user data, the received ECC parity, and at least one bit from the received syncmark. The decoder is configured to decode one of the sequence or the inverted sequence.