Patents by Inventor Hajime Matsumoto

Hajime Matsumoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200321438
    Abstract: A gallium nitride substrate comprising a first main surface and a second main surface opposite thereto, wherein the first main surface is a non-polar or semi-polar plane, a dislocation density measured by a room-temperature cathode luminescence method in the first main surface is 1×104 cm?2 or less, and an averaged dislocation density measured by a room-temperature cathode luminescence method in an optional square region sizing 250 ?m×250 ?m in the first main plan is 1×106 cm?2 or less.
    Type: Application
    Filed: June 19, 2020
    Publication date: October 8, 2020
    Applicant: MITSUBISHI CHEMICAL CORPORATION
    Inventors: Yusuke Tsukada, Shuichi Kubo, Kazunori Kamada, Hideo Fujisawa, Tatsuhiro Ohata, Hirotaka Ikeda, Hajime Matsumoto, Yutaka Mikawa
  • Patent number: 10734485
    Abstract: The main purpose of the present invention is to provide: a nonpolar or semipolar GaN substrate, in which a nitride semiconductor crystal having a low stacking fault density can be epitaxially grown on the main surface of the substrate, and a technique required for the production of the substrate. This invention provides: a method for manufacturing an M-plane GaN substrate comprising; forming a mask pattern having a line-shaped opening parallel to an a-axis of a C-plane GaN substrate on an N-polar plane of the C-plane GaN substrate, growing a plane-shape GaN crystal of which thickness direction is an m-axis direction from the opening of the mask pattern by an ammonotharmal method, and cutting out the M-plane GaN substrate from the plane-shape GaN crystal.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: August 4, 2020
    Assignee: MITSUBISHI CHEMICAL CORPORATION
    Inventors: Yusuke Tsukada, Shuichi Kubo, Kazunori Kamada, Hideo Fujisawa, Tatsuhiro Ohata, Hirotaka Ikeda, Hajime Matsumoto, Yutaka Mikawa
  • Patent number: 10679711
    Abstract: According to one embodiment, a memory system includes first, second, and third ICs. The first IC includes a non-volatile semiconductor memory. The second IC includes a controller configured to control the non-volatile semiconductor memory. The third IC is configured to receive an external first power supply voltage and generate a second power supply voltage. The third IC is connected to the second IC via an interface according to a serial communication standard. A temperature sensor element is connected to the third IC.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: June 9, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Hajime Matsumoto
  • Patent number: 10535897
    Abstract: The object of the present invention is to provide the gelatinous, molten salt having a high ion-conductivity and an excellent heat resistance. The object of the present invention can be solved by the inorganic nanofibers having a functional group which inter-molecularly interacts with the molten salt on the surface thereof, and the molten salt composition comprising molten salt; or the method for increasing a viscosity of liquid molten salt characterized in that the inorganic nanofibers having a functional group which inter-molecularly interacts with the molten salt in the surface thereof is added to the liquid molten salt.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: January 14, 2020
    Assignee: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Hidetoshi Matsumoto, Takahiro Yuki, Yoichi Tominaga, Hajime Matsumoto, Keigo Kubota
  • Publication number: 20190295663
    Abstract: According to one embodiment, a memory system includes first, second, and third ICs. The first IC includes a non-volatile semiconductor memory. The second IC includes a controller configured to control the non-volatile semiconductor memory. The third IC is configured to receive an external first power supply voltage and generate a second power supply voltage. The third IC is connected to the second IC via an interface according to a serial communication standard. A temperature sensor element is connected to the third IC.
    Type: Application
    Filed: August 6, 2018
    Publication date: September 26, 2019
    Inventor: Hajime Matsumoto
  • Publication number: 20190165420
    Abstract: The present invention provides a magnesium secondary cell comprising a positive electrode, a negative electrode releasing magnesium ions, and a nonaqueous electrolyte. The nonaqueous electrolyte comprises a solvent and a magnesium sulfonamide salt represented by formula (I) below, Mg[X1—SO2—N—SO2—X2]2??(I) wherein X1 and X2 are identical or different and each represents CpF2p+1, or X1 and X2 are taken together to represent CqF2q, wherein p is 0, 1, 2, or 3, and q is 2, 3, or 4. The solvent is a mixed solvent comprising a sulfone-based solvent and an ether- or thioether-based solvent, or the solvent is a solvent comprising a sulfone moiety and an ether or thioether moiety.
    Type: Application
    Filed: February 28, 2017
    Publication date: May 30, 2019
    Applicant: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Hajime MATSUMOTO, Rie OOYABU, Keigo KUBOTA, Kazumi TAKEDA
  • Patent number: 10175898
    Abstract: A semiconductor device includes a connector connectable to a host, a power supply circuit which includes an input portion that receives first power from the host via the connector, an output portion, and a switch that is connected to the input portion and the output portion and controls whether to supply the first power to the output portion, the power supply circuit generating second power and third power from the first power, a semiconductor memory which receives the second power from the output portion, and a controller which receives the third power from the output portion and controls the semiconductor memory. The power supply circuit turns off the switch and stops supply of power to the semiconductor memory and the controller when the second power exceeds a first value or when the third power exceeds a second value.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: January 8, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hajime Matsumoto, Toyokazu Eguchi, Hitoshi Yagisawa
  • Publication number: 20180337426
    Abstract: The object of the present invention is to provide the gelatinous, molten salt having a high ion-conductivity and an excellent heat resistance. The object of the present invention can be solved by the inorganic nanofibers having a functional group which inter-molecularly interacts with the molten salt on the surface thereof, and the molten salt composition comprising molten salt; or the method for increasing a viscosity of liquid molten salt characterized in that the inorganic nanofibers having a functional group which inter-molecularly interacts with the molten salt in the surface thereof is added to the liquid molten salt.
    Type: Application
    Filed: February 26, 2016
    Publication date: November 22, 2018
    Applicant: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Hidetoshi MATSUMOTO, Takahiro YUKI, Yoichi TOMINAGA, Hajime MATSUMOTO, Keigo KUBOTA
  • Patent number: 10121519
    Abstract: A semiconductor device includes a connector configured for connection to a host, a power circuit supplied with a first voltage from the host via the connector, the power circuit including first and second channels configured to generate second and third voltages, respectively, from the first voltage, a semiconductor memory supplied with the second voltage via the first channel, and a controller for the semiconductor memory, supplied with the third voltage via the second channel. When the first voltage is less than a first threshold, the power circuit turns off the first channel and the second channel.
    Type: Grant
    Filed: September 3, 2017
    Date of Patent: November 6, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Toyokazu Eguchi, Hajime Matsumoto
  • Publication number: 20180286465
    Abstract: A semiconductor device includes a connector configured for connection to a host, a power circuit supplied with a first voltage from the host via the connector, the power circuit including first and second channels configured to generate second and third voltages, respectively, from the first voltage, a semiconductor memory supplied with the second voltage via the first channel, and a controller for the semiconductor memory, supplied with the third voltage via the second channel. When the first voltage is less than a first threshold, the power circuit turns off the first channel and the second channel.
    Type: Application
    Filed: September 3, 2017
    Publication date: October 4, 2018
    Inventors: Toyokazu EGUCHI, Hajime MATSUMOTO
  • Publication number: 20180285001
    Abstract: A semiconductor device includes a connector connectable to a host, a power supply circuit which includes an input portion that receives first power from the host via the connector, an output portion, and a switch that is connected to the input portion and the output portion and controls whether to supply the first power to the output portion, the power supply circuit generating second power and third power from the first power, a semiconductor memory which receives the second power from the output portion, and a controller which receives the third power from the output portion and controls the semiconductor memory. The power supply circuit turns off the switch and stops supply of power to the semiconductor memory and the controller when the second power exceeds a first value or when the third power exceeds a second value.
    Type: Application
    Filed: June 5, 2018
    Publication date: October 4, 2018
    Inventors: Hajime MATSUMOTO, Toyokazu EGUCHI, Hitoshi YAGISAWA
  • Patent number: 10070056
    Abstract: An omnidirectional camera system includes an omnidirectional camera that acquires an omnidirectional image by capturing using a fish-eye lens and an image processing device which displays the plurality of partial images which are cut out from the omnidirectional image side by side on one screen, in which the omnidirectional camera performs luminance adjustment with respect to the omnidirectional image, and the image processing device performs gradation adjustment processing in each partial image with respect to the plurality of partial images.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: September 4, 2018
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Hajime Matsumoto, Takamasa Yokoyama
  • Patent number: 10001936
    Abstract: A semiconductor device includes a connector connectable to a host, a power supply circuit which includes an input portion that receives first power from the host via the connector, an output portion, and a switch that is connected to the input portion and the output portion and controls whether to supply the first power to the output portion, the power supply circuit generating second power and third power from the first power, a semiconductor memory which receives the second power from the output portion, and a controller which receives the third power from the output portion and controls the semiconductor memory. The power supply circuit turns off the switch and stops supply of power to the semiconductor memory and the controller when the second power exceeds a first value or when the third power exceeds a second value.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: June 19, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Hajime Matsumoto, Toyokazu Eguchi, Hitoshi Yagisawa
  • Patent number: 9969933
    Abstract: The present invention relates to a phosphor represented by the Formula [1]: MaSrbCacAldSieNf, wherein the phosphor includes phosphor particles in which single crystallites are three-dimensionally coupled to each other, the phosphor particles include a crystal grain boundary triple point, and [a total number of the crystal grain boundary triple points (A)]/[the number of the phosphor particles (B)] is 1.0 or less.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: May 15, 2018
    Assignee: MITSUBISHI CHEMICAL CORPORATION
    Inventor: Hajime Matsumoto
  • Publication number: 20180046390
    Abstract: A semiconductor device includes a connector connectable to a host, a power supply circuit which includes an input portion that receives first power from the host via the connector, an output portion, and a switch that is connected to the input portion and the output portion and controls whether to supply the first power to the output portion, the power supply circuit generating second power and third power from the first power, a semiconductor memory which receives the second power from the output portion, and a controller which receives the third power from the output portion and controls the semiconductor memory. The power supply circuit turns off the switch and stops supply of power to the semiconductor memory and the controller when the second power exceeds a first value or when the third power exceeds a second value.
    Type: Application
    Filed: February 7, 2017
    Publication date: February 15, 2018
    Inventors: Hajime MATSUMOTO, Toyokazu EGUCHI, Hitoshi YAGISAWA
  • Publication number: 20170294675
    Abstract: This invention provides a non-aqueous electrolyte magnesium secondary battery comprising a positive electrode, a negative electrode, a separator, and a non-aqueous electrolyte, the non-aqueous electrolyte comprising [N(SO2CF3)2]? as an anion, and Mg2+ and/or an organic onium cation as a cation.
    Type: Application
    Filed: October 8, 2015
    Publication date: October 12, 2017
    Applicant: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Keigo KUBOTA, Kenichi TERAMOTO, Rie OOYABU, Hajime MATSUMOTO
  • Publication number: 20170256820
    Abstract: The present invention provides an ionic liquid or plastic crystal comprising an anion and a cation, the anion comprising [C(SO2F)3]?, and the cation comprising at least one member selected from the group consisting of 1-ethyl-3-methylimidazolium ([EMI]+), N,N-diethyl-N-methyl-(2-methoxyethyl)ammonium ([DEME]+), N-methyl-N-propylpyrrolidinium ([Py13]+), N-methyl-N-propylpiperidinium ([PP13]+), tetramethylammonium ([N1111]+), tetraethylammonium ([N2222]+), trimethylhexylammonium ([N6111]+), triethylhexylammonium ([N6222]+), N-methyl-ethylpyrrolidinium ([Py12]+), 1-butyl-3-methylimidazolium ([C4mim]+), and 1-hexyl-3-methylimidazolium ([C6mim]+).
    Type: Application
    Filed: August 28, 2015
    Publication date: September 7, 2017
    Applicant: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Hajime MATSUMOTO, Junji MIZUKADO, Peng-cheng WANG
  • Publication number: 20170200789
    Abstract: The main purpose of the present invention is to provide: a nonpolar or semipolar GaN substrate, in which a nitride semiconductor crystal having a low stacking fault density can be epitaxially grown on the main surface of the substrate, and a technique required for the production of the substrate. This invention provides: a method for manufacturing an M-plane GaN substrate comprising; forming a mask pattern having a line-shaped opening parallel to an a-axis of a C-plane GaN substrate on an N-polar plane of the C-plane GaN substrate, growing a plane-shape GaN crystal of which thickness direction is an m-axis direction from the opening of the mask pattern by an ammonotharmal method, and cutting out the M-plane GaN substrate from the plane-shape GaN crystal.
    Type: Application
    Filed: March 29, 2017
    Publication date: July 13, 2017
    Applicant: MITSUBISHI CHEMICAL CORPORATION
    Inventors: Yusuke TSUKADA, Shuichi KUBO, Kazunori KAMADA, Hideo FUJISAWA, Tatsuhiro OHATA, Hirotaka IKEDA, Hajime MATSUMOTO, Yutaka MlKAWA
  • Patent number: 9673046
    Abstract: The invention provides a nonpolar or semipolar GaN substrate, in which a nitride semiconductor crystal having a low stacking fault density can be epitaxially grown on the main surface of the substrate, and a method for manufacturing an M-plane GaN substrate by forming a mask pattern having a line-shaped opening parallel to an a-axis of a C-plane GaN substrate on an N-polar plane of the C-plane GaN substrate, growing a plane-shape GaN crystal of which thickness direction is an m-axis direction from the opening of the mask pattern by an ammonothermal method, and cutting out the M-plane GaN substrate from the plane-shape GaN crystal.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: June 6, 2017
    Assignee: MITSUBISHI CHEMICAL CORPORATION
    Inventors: Yusuke Tsukada, Shuichi Kubo, Kazunori Kamada, Hideo Fujisawa, Tatsuhiro Ohata, Hirotaka Ikeda, Hajime Matsumoto, Yutaka Mikawa
  • Publication number: 20170137709
    Abstract: The present invention relates to a phosphor represented by the Formula [1]: MaSrbCacAldSieNf, wherein the phosphor includes phosphor particles in which single crystallites are three-dimensionally coupled to each other, the phosphor particles include a crystal grain boundary triple point, and [a total number of the crystal grain boundary triple points (A)]/[the number of the phosphor particles (B)] is 1.0 or less.
    Type: Application
    Filed: January 31, 2017
    Publication date: May 18, 2017
    Applicant: Mitsubishi Chemical Corporation
    Inventor: Hajime MATSUMOTO