Abstract: A semiconductor structure and a fabrication method are provided. The fabrication method includes: providing a substrate; forming a gate dielectric layer on the substrate; forming a dielectric barrier layer structure on the gate dielectric layer, a first silicon source gas being used to dope silicon in the dielectric barrier layer structure; forming a work function layer on the dielectric barrier layer structure; forming a gate barrier layer structure on the work function layer, a second silicon source gas being used to dope silicon in the gate barrier layer structure; and forming a gate electrode layer on the gate barrier layer structure.

Abstract: A semiconductor structure and a fabrication method are provided. The fabrication method includes: providing a substrate; forming a dielectric layer with an opening on the substrate; forming a first barrier layer on sidewall and bottom surfaces of the opening, the first barrier layer being doped by manganese; and forming a metal interconnect on the first barrier layer, the metal interconnect being located within the opening.

Abstract: A method for fabricating an interconnection structure includes providing a substrate, forming a dielectric layer on the substrate, forming a conductive structure in the dielectric layer, forming a cap layer doped with silicon on the conductive structure and the dielectric layer, and performing an annealing process on the conductive structure and the cap layer. During the annealing process, the silicon ions in the cap layer react with the material of the conductive structure and form chemical bonds. As such, the connection strength between the cap layer and the conductive structure is improved, which is conducive to suppressing electro migration in the formed interconnection structure. Therefore, the reliability of the formed interconnection structure is improved.

Abstract: A method for manufacturing a semiconductor device includes providing a semiconductor structure having a semiconductor substrate, a dielectric layer on the semiconductor substrate, and a hardmask on a second portion of the dielectric layer while exposing a first portion of the dielectric layer; forming a copolymer on the semiconductor structure; performing an annealing treatment such that the copolymer forms a staggered configuration of a first monomer and a second monomer; removing the first monomer; performing a first etching process on the first portion using the second monomer as a mask to form a first trench extending to the semiconductor substrate; removing the second monomer and the first hardmask; and epitaxially growing a first semiconductor fin in the first trench.

Abstract: Methods and systems disclosed herein use acoustic energy to determine a gap between a wafer and an integrated circuit (IC) processing system and/or determine a thickness of a material layer of the wafer during IC processing implemented by the IC processing system. An exemplary method includes emitting acoustic energy through a substrate and a material layer disposed thereover. The substrate is positioned within an IC processing system. The method further includes receiving reflected acoustic energy from a surface of the substrate and a surface of the material layer disposed thereover and converting the reflected acoustic energy into electrical signals. The electrical signals indicate a thickness of the material layer.

Abstract: In accordance with various embodiments of the disclosed subject matter, a shallow trench isolation structure and a fabricating method thereof are provided. The method for forming the shallow trench isolation structure may include: providing a semiconductor substrate; forming a shallow trench in the semiconductor substrate; forming a first insulating layer on a surface of the semiconductor substrate and in the shallow trench, a portion of the first insulating layer in the shallow trench includes an opening; etching the first insulating layer to increase a width of the opening; after etching the first insulating layer, performing a plasma treatment to an exposed surface of the first insulating layer; after the plasma treatment, cleaning the surface of the first insulating layer; and after cleaning the surface of the first insulating layer, filling a second insulating layer into the shallow trench.

Abstract: A three-dimensional convertor includes a housing and a socket interior arranged inside the housing. The socket interior includes clapboards, a live wire plug bush conductive sheet, a naught wire plug bush conductive sheet and an earth wire plug bush conductive sheet. The clapboards include a first clapboard, a second clapboard, a third clapboard and a fourth clapboard which are sequentially stacked. The naught wire plug bush conductive sheet is located between the first clapboard and the second clapboard, the earth wire plug bush conductive sheet is located between the second clapboard and the third clapboard, the live wire plug bush conductive sheet is located between the third clapboard and the fourth clapboard. The housing includes at least two jack surfaces each of which is provided with a jack. The jack is corresponding to the live wire plug bush conductive sheet, the naught wire plug bush conductive sheet and the earth wire plug bush conductive sheet.

Abstract: A semiconductor structure and a fabrication method are provided. The fabrication method includes: providing a substrate; forming a dielectric layer with an opening on the substrate; forming a first barrier layer on sidewall and bottom surfaces of the opening, the first barrier layer being doped by manganese; and forming a metal interconnect on the first barrier layer, the metal interconnect being located within the opening.

Abstract: A semiconductor structure and a fabrication method are provided. The fabrication method includes: providing a substrate; forming a gate dielectric layer on the substrate; forming a dielectric barrier layer structure on the gate dielectric layer, a first silicon source gas being used to dope silicon in the dielectric barrier layer structure; forming a work function layer on the dielectric barrier layer structure; forming a gate barrier layer structure on the work function layer, a second silicon source gas being used to dope silicon in the gate barrier layer structure; and forming a gate electrode layer on the gate barrier layer structure.

Abstract: A method for manufacturing a semiconductor device includes providing a semiconductor structure having a semiconductor substrate, a dielectric layer on the semiconductor substrate, and a hardmask on a second portion of the dielectric layer while exposing a first portion of the dielectric layer; forming a copolymer on the semiconductor structure; performing an annealing treatment such that the copolymer forms a staggered configuration of a first monomer and a second monomer; removing the first monomer; performing a first etching process on the first portion using the second monomer as a mask to form a first trench extending to the semiconductor substrate; removing the second monomer and the first hardmask; and epitaxially growing a first semiconductor fin in the first trench.

Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate having a metal gate structure formed on the semiconductor substrate; forming a first dielectric layer covering a side surface of the metal gate structure on the semiconductor substrate; forming a cap layer on the metal gate structure; etching a top portion of the first dielectric layer using the cap layer as an etching mask; forming a protective sidewall spacer on a side surface of the cap layer and a side surface of a portion of the first dielectric layer under the cap layer; forming a second dielectric layer to cover the cap layer, the protective sidewall spacer and a top surface of the etched first dielectric layer; forming at least a first through-hole in the second dielectric layer; and forming a first conductive via in the first through-hole.

Abstract: A method for fabricating an interconnection structure includes providing a substrate, forming a dielectric layer on the substrate, forming a conductive structure in the dielectric layer, forming a cap layer doped with silicon on the conductive structure and the dielectric layer, and performing an annealing process on the conductive structure and the cap layer. During the annealing process, the silicon ions in the cap layer react with the material of the conductive structure and form chemical bonds. As such, the connection strength between the cap layer and the conductive structure is improved, which is conducive to suppressing electro migration in the formed interconnection structure. Therefore, the reliability of the formed interconnection structure is improved.

Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate having a metal gate structure formed on the semiconductor substrate; forming a first dielectric layer covering a side surface of the metal gate structure on the semiconductor substrate; forming a cap layer on the metal gate structure; etching a top portion of the first dielectric layer using the cap layer as an etching mask; forming a protective sidewall spacer on a side surface of the cap layer and a side surface of a portion of the first dielectric layer under the cap layer; forming a second dielectric layer to cover the cap layer, the protective sidewall spacer and a top surface of the etched first dielectric layer; forming at least a first through-hole in the second dielectric layer; and forming a first conductive via in the first through-hole.

Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate having a metal gate structure formed on the semiconductor substrate; forming a first dielectric layer covering a side surface of the metal gate structure on the semiconductor substrate; forming a cap layer on the metal gate structure; etching a top portion of the first dielectric layer using the cap layer as an etching mask; forming a protective sidewall spacer on a side surface of the cap layer and a side surface of a portion of the first dielectric layer under the cap layer; forming a second dielectric layer to cover the cap layer, the protective sidewall spacer and a top surface of the etched first dielectric layer; forming at least a first through-hole in the second dielectric layer; and forming a first conductive via in the first through-hole.

Abstract: A dielectric ceramic material includes the composite ceramic powder of BaTiO3 and Ba2LiTa5O15, or BaTiO3 and Ba2LiNb5O15 that are based on the oxides of BaO, TiO2, Li2O and Ta2O5, or BaO, TiO2, Li2O and Nb2O5 as initial powder materials prepared subject to a respective predetermined percentage. This dielectric ceramic material simply uses simple binary oxides as initial powder materials that are easy to obtain and inexpensive, and that eliminate the complicated manufacturing process of synthesizing BaTiO3, Ba2LiTa5O15 or Ba2LiNb5O15, making the whole process more simple and the manufacturing cost more cheaper and preventing the formation of other compounds.

Abstract: A system and method for determining clearance between a fabrication tool and a workpiece is provided. In an exemplary embodiment, the method includes receiving a substrate within a tool such that a gap is defined there between. A transducer disposed on a bottom surface of the substrate opposite the gap provides an acoustic signal that is conducted through the substrate. The transducer also receives a first echo from a top surface of the substrate that defines the gap and a second echo from a bottom surface of the tool that further defines the gap. A width of the gap is measured based on the first echo and the second echo. In some embodiments, the bottom surface of the tool is a bottom surface of a nozzle, and the nozzle provides a liquid or a gas in the gap while the transducer is receiving the first and second echoes.

Abstract: A method for forming a semiconductor structure is provided. The method includes providing a substrate; and forming an ultra-low-dielectric-constant (ULK) dielectric layer on a surface of the substrate. The method also includes etching the ultra-low-dielectric-constant dielectric layer to form a trench in the ultra-low-dielectric-constant dielectric layer; and performing an inert plasma treatment process on a side surface of the trench. Further, the method includes performing a carbonization process on the side surface of the trench; and performing a nitridation process on the side surface of the trench to form a SiCNH layer on the side surface of the trench.

Abstract: In accordance with various embodiments of the disclosed subject matter, a shallow trench isolation structure and a fabricating method thereof are provided. The method for forming the shallow trench isolation structure may include: providing a semiconductor substrate; forming a shallow trench in the semiconductor substrate; forming a first insulating layer on a surface of the semiconductor substrate and in the shallow trench, a portion of the first insulating layer in the shallow trench includes an opening; etching the first insulating layer to increase a width of the opening; after etching the first insulating layer, performing a plasma treatment to an exposed surface of the first insulating layer; after the plasma treatment, cleaning the surface of the first insulating layer; and after cleaning the surface of the first insulating layer, filling a second insulating layer into the shallow trench.

Abstract: A method for forming an interconnect device is provided by the present disclosure. The method includes providing a dielectric layer on a substrate, forming openings in the dielectric layer to expose a portion of a surface of the substrate at a bottom of each opening and forming a metal layer to fill up the openings. The method also includes forming a semiconductor cover layer on the metal layer and on the dielectric layer, and performing a thermal annealing reaction to convert portions of the semiconductor cover layer that are on the metal layer into a metal capping layer. The method further includes performing a nitridation process on the metal capping layer and a remaining semiconductor cover layer to convert the metal capping layer into a metal nitride capping layer and the remaining semiconductor cover layer into a semiconductor nitride layer.

Abstract: The present disclosure provides a method for forming a semiconductor device. The method includes providing a substrate and forming a dielectric layer on the substrate by a deposition process using reactant gases. The reactant gases include a silicon-source gas and an oxygen-source gas under a radio-frequency (RF) power. The deposition process performed for a total deposition time to form the dielectric layer is divided into a first time length, a second time length and a third time length. The RF power of the deposition process in the first time length is a first power, the first power gradually increases from the first power to a second power in the second time length, the RF power in the third time length is the second power, and the first power is less than the second power.