Abstract: A package includes a memory stack attached to a logic device, the memory stack including first memory structures, a first redistribution layer over and electrically connected to the first memory structures, second memory structures on the first redistribution layer, a second redistribution layer over and electrically connected to the second memory structures, and first metal pillars on the first redistribution layer and adjacent the second memory structures, the first metal pillars electrically connecting the first redistribution layer and the second redistribution layer, wherein each first memory structure of the first memory structures includes a memory die comprising first contact pads and a peripheral circuitry die comprising second contact pads, wherein the first contact pads of the memory die are bonded to the second contact pads of the peripheral circuitry die.

Abstract: A flexible tube includes a first connecting portion and a second connecting section. The second connecting section and the first connecting section are integrally connected to each other. The first connecting section has a first end surface, and the second connecting section has a second end surface, wherein there is an acute angle between the first end surface and the second end surface.

Abstract: A power supply is provided. The power supply includes a power supply circuit and a control circuit. The power supply circuit includes a voltage converter and multiple point-of-load circuits. The voltage converter generates a third voltage according to a first voltage. The load point-of-load circuits generate at least one second voltage and at least one state signal according to the third voltage. The at least one second voltage is suitable for supplying power to a load. The control circuit is coupled to the power supply circuit. The control circuit determines whether a single event latch-up occurs in the power supply circuit according to the at least one state signal. When the single event latch-up occurs in the power supply circuit, the control circuit switches off the power supply circuit to stop generating the at least one second voltage and the at least one state signal.

Abstract: In an embodiment, a method includes: aligning a first package component with a second package component, the first package component having a first region and a second region, the first region including a first conductive connector, the second region including a second conductive connector; performing a first laser shot on a first portion of a top surface of the first package component, the first laser shot reflowing the first conductive connector of the first region, the first portion of the top surface of the first package component completely overlapping the first region; and after performing the first laser shot, performing a second laser shot on a second portion of the top surface of the first package component, the second laser shot reflowing the second conductive connector of the second region, the second portion of the top surface of the first package component completely overlapping the second region.

Abstract: A method for wireless communication performed by a user equipment (UE) is provided. The UE includes a plurality of antenna panels. The method includes transmitting, to a Base Station (BS), a UE capability message that includes a number of the plurality of antenna panels; and transmitting, to the BS, a panel report that includes information of the plurality of antenna panels, the information associated with at least one of a Synchronization Signal Block (SSB) and a Channel State Information Reference Signal (CSI-RS).

Abstract: The present disclosure relates to a method for producing vinyl acetate, comprising a vinyl acetate synthesis process, a vinyl acetate refining process and a separation process of vinyl acetate and ethyl acetate, including an acetic acid evaporator, an oxygen mixer, a vinyl acetate synthesis reactor, a first gas separating tower, a second gas separating tower, a recovered gas compressor, a water washing tower, an absorption tower and a desorption tower, a recycling gas compressor; the vinyl acetate refining process comprising an acetic acid tower, a crude VAC tower, and a fine VAC tower, a rectifying tower, an ethyl acetate tower, a water phase receiving tank, an extracting and rectifying tower and an ethyl acetate phase separator.

Abstract: A computer implemented method for managing the scope of permissions granted by users to application that includes collecting a set of permissions for an application from an application provider publication; and collecting a process flow for functional steps of the application from a review of the application that is published on a product review type publication. The computer implemented method further includes dividing the functional steps of the application into a plurality of journeys, each of said plurality of journeys having a function associated with a stage of a functional step from a perspective of a user; and matching permissions from the set of permissions for each journey of said plurality of journeys to provide matched permissible permissions to journeys stored in a customer journey store.

Abstract: Provided are a water-soluble Pd(II) complex, a synthesis method thereof and use thereof as a catalytic precursor. The complex has a chemical name, ammonium dinitrooxalato palladium (II), and a molecular formula of (NH4)2[Pd(NO2)2(C2O4)]·nH2O (n is the number of crystal water). The Pd(II) complex is synthesized by using PdCl2 or [Pd(NH3)2Cl2] as a starting material which is firstly converted into [Pd(NH3)4]Cl2 in ammonium hydroxide, followed by a chemical reaction between [Pd(NH3)4]Cl2 and excessive NaNO2 to produce trans-[Pd(NH3)2(NO2)2] via ligand substitution mechanism, and finally dissolving trans-[Pd(NH3)2(NO2)2] in an aqueous solution of oxalic acid leads to the formation of the target product (NH4)2[Pd(NO2)2(C2O4)]·2H2O. The complex does not contain chlorine and other elements that are harmful to a catalyst, is readily soluble in water and has a low thermal decomposition temperature.

Abstract: A method for forming a semiconductor device is provided. The method includes forming a plurality of first channel nanostructures and a plurality of second channel nanostructures in an n-type device region and a p-type device region of a substrate, respectively, and sequentially depositing a gate dielectric layer, an n-type work function metal layer, and a cap layer surrounding each of the first and second channel nanostructures. The cap layer merges in first spaces between adjacent first channel nanostructures and merges in second spaces between adjacent second channel nanostructures. The method further includes selectively removing the cap layer and the n-type work function metal layer in the p-type device region, and depositing a p-type work function metal layer over the cap layer in the n-type device region and the gate dielectric layer in the p-type device region. The p-type work function metal layer merges in the second spaces.

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a first channel structure configured to transport charge carriers within a first transistor device and a first gate electrode layer wrapping around the first channel structure. A second channel structure is configured to transport charge carriers within a second transistor device. A second gate electrode layer wraps around the second channel structure. The second gate electrode layer continuously extends from around the second channel structure to cover the first gate electrode layer. A third channel structure is configured to transport charge carriers within a third transistor device. A third gate electrode layer wraps around the third channel structure. The third gate electrode layer continuously extends from around the third channel structure to cover the second gate electrode layer.

Abstract: A semiconductor device has a conductive via laterally separated from the semiconductor, an encapsulant between the semiconductor device and the conductive via, and a mark. The mark is formed from characters that are either cross-free characters or else have a overlap count of less than two. In another embodiment the mark is formed using a wobble scan methodology. By forming marks as described, defects from the marking process may be reduced or eliminated.

Abstract: A semiconductor device includes a first dielectric layer, a stack of semiconductor layers disposed over the first dielectric layer, a gate structure wrapping around each of the semiconductor layers and extending lengthwise along a direction, and a dielectric fin structure and an isolation structure disposed on opposite sides of the stack of semiconductor layers and embedded in the gate structure. The dielectric fin structure has a first width along the direction smaller than a second width of the isolation structure along the direction. The isolation structure includes a second dielectric layer extending through the gate structure and the first dielectric layer, and a third dielectric layer extending through the first dielectric layer and disposed on a bottom surface of the gate structure and a sidewall of the first dielectric layer.

Abstract: A computer-implemented method for aligning a sensor to reference coordinate system includes initiating a plurality of threads, each thread executes simultaneously and independent of each other. A first thread parses data received from the sensor and stores the parsed data in a data buffer. A second thread computes an alignment transformation using the parsed data to determine alignment between the sensor and the reference coordinate system. The computing includes checking that the data buffer contains at least predetermined amount of data. If at least the predetermined amount of data exists, an intermediate result is computed using the parsed data in the data buffer; otherwise, the second thread waits for the first thread to add more data to the data buffer. The second thread outputs the intermediate result into the data buffer. A third thread outputs the alignment transformation, in response to completion of alignment computations.

Abstract: A chip-level software and hardware cooperative relay protection device is provided. The device includes: a control chip, wherein a first control unit, a second control unit, and multiple logic circuits are integrated on the control chip; and the logic circuits perform microsecond-level rapid calculation on electrical signals of a protected electrical device, obtain fault feature parameters of the protected electrical device are and transmit same to the first control unit, then perform millisecond-level real-time protection logic determination according to the fault feature parameters of the protected electrical device to obtain relay protection results of the protected electrical device, and protect the protected electrical device by controlling an external relay according to the relay protection results.

Abstract: A vehicle includes a system performing a method of operating a camera for the vehicle. The camera is configured to capture an image. The processor is configured to query the camera to obtain an intrinsic parameter of the camera, estimate a unified parameter based on the intrinsic parameter of the camera, and perform at least one application on the image using the unified parameter.

Abstract: Processing methods are described that include forming a group of LED structures on a substrate layer to form a patterned LED substrate. The methods also include depositing a light absorption material on the pattered LED substrate, where the light absorption material includes at least one photocurable compound and at least one ultraviolet light absorbing material. The methods further include exposing a portion of the light absorption material to patterned light, wherein the patterned light cures the exposed portion of the light absorption material into pixel isolation structures. The methods additionally include depositing an isotropic layer on a top portion and a side portion of the pixel isolation structures, where the LED structures are substantially free of the as-deposited isotropic light reflecting layer.

Abstract: A light-emitting device is provided. The light-emitting device includes a display panel including a substrate and a plurality of scan lines disposed on the substrate and extending in a first direction, a backlight module disposed under the display panel, and an optical film disposed above the backlight module and including a plurality of light-blocking portions and a plurality of light-transmission portions which are arranged alternately. The light blocking portions extend in a second direction, and the first direction and the second direction are not parallel.

Abstract: A fan braking structure includes a fan including a frame having an upright bearing cup, and a fan impeller having a vertical rotating shaft pivotally received in the bearing cup and provided at a free end with a groove; a braking structure located at a lower part of the bearing cup and including a brake plate and an electromagnet, and the brake plate being provided at one side with a protruded brake pin and at another side with a magnetic member; and an elastic element disposed between and pressed against the brake plate and the electromagnet. When the fan is powered off, the electromagnet is energized and produces magnetic poles that magnetically repel the magnetic member, such that the brake pin is pushed by a magnetic force and the elastic element toward the rotating shaft to engage with the groove, causing the fan to brake and stop rotating inertially.

Abstract: A fan brake structure includes a fan and a brake device. The fan has a frame body, a fan impeller and a stator. The brake device is disposed under a bottom of a bearing cup. The brake device has a driving member, a brake member and an elastic member. The elastic member abuts against one end of the brake member. The other end of the brake member has a boss body. The driving member has a spiral rail. When the driving member rotates, the boss body moves along the spiral rail, whereby the brake member linearly reciprocally moves upward to brake the fan impeller or linearly reciprocally moves downward to release the fan impeller from the braking.