Abstract: The present application relates to a paper picture frame including a central rectangular portion and four rectangular tubular frame sections extending along four margins of the central rectangular portion at the rear surface thereof. The paper picture frame further includes a paper stand for holding the paper picture frame on a flat surface. The paper stand may be in the form of a triangular tubular structure formed by a base panel, a first side panel, and a support panel. A second side panel extends from the base panel over the support panel, and has a terminating end extending beyond the first side panel. A blank for forming the paper picture frame and a method for holding a picture in the paper picture frame supported on the paper stand are also disclosed.

Abstract: The present application relates to a paper picture frame including a central rectangular portion and four rectangular tubular frame sections extending along four margins of the central rectangular portion at the rear surface thereof. The paper picture frame further includes a paper stand for holding the paper picture frame on a flat surface. The paper stand may be in the form of a triangular tubular structure formed by a base panel, a first side panel, and a support panel. A second side panel extends from the base panel over the support panel, and has a terminating end extending beyond the first side panel. A blank for forming the paper picture frame and a method for holding a picture in the paper picture frame supported on the paper stand are also disclosed.

Abstract: A blank for forming a printed sheet with foldable frame includes a blank body having front and rear surfaces, a central rectangular portion formed thereon with a print on the front surface. The blank further includes four wing portions extending from the four margins of the central rectangular portion and the four wing portions are foldable into four rectangular tubular frame sections. Twelve locking mechanisms are used to lock the four frame sections in a folded position. A method of forming the printed sheet with foldable frame is also disclosed.

Abstract: A blank for forming a printed sheet with foldable frame includes a blank body having front and rear surfaces, a central rectangular portion formed thereon with a print on the front surface. The blank further includes four wing portions extending from the four margins of the central rectangular portion and the four wing portions are foldable into four rectangular tubular frame sections. Twelve locking mechanisms are used to lock the four frame sections in a folded position. A method of forming the printed sheet with foldable frame is also disclosed.

Abstract: A blank for forming a one-piece picture frame with picture includes a blank body having front and rear surfaces, a central rectangular picture portion formed thereon with a picture on the front surface. The blank further includes four wing portions extending from the four margins of the rectangular picture portion and the four wing portions are foldable into four rectangular tubular frame sections. Twelve locking mechanisms are used to lock the four frame sections in a folded position. A method of forming the picture frame with picture is also disclosed.

Abstract: A blank for forming a one-piece picture frame with picture includes a blank body having front and rear surfaces, a central rectangular picture portion formed thereon with a picture on the front surface. The blank further includes four wing portions extending from the four margins of the rectangular picture portion and the four wing portions are foldable into four rectangular tubular frame sections. Twelve locking mechanisms are used to lock the four frame sections in a folded position. A method of forming the picture frame with picture is also disclosed.

Abstract: Embodiments disclosed herein relate to an optical disc drive test. In one embodiment, an optical disc drive of a host electronic device performs a test on itself. The host electronic device requests information about the test from the optical disc drive. The optical disc drive reports information about the test in response to the request.

Abstract: A digital control loop within power switchers and the like includes a sliding error sampler pulse width modulation timing variably setting a number of clock cycles relative to a digital pulse width modulator output trailing edge for loading control variables for a filter. A computation time for the proportional-integral-derivative filter is predicted based on an average for previous digital pulse width modulator outputs, computed within the integral path for the previous loop iteration. A margin is added to accommodate transient conditions accelerating the trailing edge of the digital pulse width modulator output, either fixed or variable depending on the previous iteration pulse width.

Abstract: A multiplexed digital proportional-integral-derivative filter receives error signal samples and operates in different states during sub-cycles of a single system cycle. A single multiplier and a single adder within the filter calculate at least portions of a proportional control signal, an integral control signal and a derivative control signal for one error signal sample during successive sub-cycles. The calculated control signal portions are aggregated to produce a filtered error signal for the respective error signal sample. The original resolution at lower cost, or increased resolution at the original cost, are achieved, as well as full programmability of loop gain with only negligible increase in loop latency.

Abstract: A DLL circuit for a semiconductor memory apparatus includes a delay line having a coarse delay chain, which has a plurality of coarse delayers connected in series and is inputted with a reference clock signal, and a plurality of fine delayers which receive output clock signals of the respective coarse delayers, and a delay control section for comparing phases of an output clock signal of a final coarse delayer among the coarse delayers with the reference clock signal and generating coarse control signals for controlling the coarse delayers and for comparing phases of an output clock signal of a fine delayer inputted with the output clock signals of the final coarse delayer, as a fine feedback clock signal, with the reference clock signal and generating fine control signals for controlling the fine delayers.

Abstract: Proportional, integral and derivative error gains within a proportional-integral-derivative filter are selected based on a magnitude of the error value and with successively higher gain values corresponding to larger ranges of error values. Coding of the error gains is selected based on one or more of: large code-dynamic-range to achieve good transient and quiescent responses; small code-step ratio to achieve smooth transitions between consecutive steps; large gain control range to satisfy the differing gain coverage requirements of the three proportional, integral and derivative error; positive and negative code symmetry with small step increment about zero; reservation of code space for dead band elimination; allocation of code space to prevent overflow/underflow during multiplying and bit-shifting; and minimum cost and power.

Abstract: Fine resolution pulse width modulation is achieved through feed-forward edge extending logic. A ring-oscillator produces phase-shifted versions of a system clock and two latches operate in parallel with the system clock output from the multiplexer clocking a first latch and a selected phase-shifted version of the system clock from the multiplexer clocking the second latch. The first latch receives a coarse output pulse equal to a selected number of clock periods as an input, while the second latch receives the output of the first latch as an input. A logic gate combines outputs from the latches to produce the output pulse having a trailing edge extended by a selected number of phase divisions.

Abstract: Testing of a wireless transceiver employs a selectively activated multi-subcarrier test vector or corresponding waveform for which all subcarriers are activated except subcarriers below a selected subcarrier fundamental and harmonics of the selected subcarrier fundamental. Use of selectively activated multi-subcarrier testing allows measurement of inter-modulation distortion, harmonic distortion, frequency response, and phase noise using a common spectrum analyzer, with individual results pinpointing sources of impairment.

Abstract: There is disclosed a radio frequency (RF) demodulation circuit comprising: 1) a first RF mixer having a first input port for receiving an in-phase RF signal having a frequency of RF and a second input port for receiving an in-phase local oscillator (LO) signal having a frequency of LO, wherein LO is approximately equal to one-half of RF, and wherein the first RF mixer generates a first intermediate frequency (IF) signal having a frequency of LO; 2) a second RF mixer having a first input port for receiving an out-of-phase RF signal having a frequency of RF and a second input port for receiving an out-of-phase local oscillator (LO) signal having a frequency of LO, and wherein the second RF mixer generates a second intermediate frequency (IF) signal having a frequency of LO; and 3) a first signal combiner for combining the first and second IF signals to generate a composite IF signal, wherein the first signal combiner combines a first leakage signal from the first RF mixer and a second leakage signal from the se

Abstract: Adjustable gain circuits (AGCs) within serial filter stages are initialized to maximum gain. The output of each AGC is then sampled and converted to digital representation for use by control logic in setting the gain for the respective AGC. The gain adjustment decision for each AGC is performed in one shot, sequentially backwards from the last AGC, such that gain may be adapted simply and quickly within a number of cycles equal to the number of AGCs. Performance is enhanced by a fast-adapting cell in which capacitances are switched into the input path and feedback loop of an amplifier to reduce direct current gain within the transfer function through charge sharing dividing down the output voltage.

Abstract: A digital control loop within power switchers and the like includes a sliding error sampler analog-to-digital converter producing an error value for a digital loop iteration. A predictor variably sets the timing for initiating analog-to-digital conversion of the current error value based on the magnitude of a previous error value for a previous loop iteration, plus margins conversion housekeeping and the step size of the next loop iteration. At a timing prior to a filter reading the error value that equals the number of clock cycles set by the predictor, a timing unit triggers the analog-to-digital conversion, reducing loop latency and improving performance.

Abstract: Dead-time gaps are inserted into one of two output transistor control signals from a digital pulse width modulator by controlling the leading and trailing edges using the same phase-division and dithering signals employed by the digital pulse width modulator. Adders add the phase select signals from the digital pulse width modulator and the dithering signal to the leading and trailing edge control signals, with the output employed by multiplexers as select controls in selecting a phase of from the phase-shifted versions of the system clock with which to clock latches controlling the leading and trailing edges.

Abstract: Data transmitter includes a first and second output nodes terminated to a first level, a controller configured to generate an off signal that is activated by logically combining first and second data during a low-power mode, a first driver configured to drive the first or second output node to a second level in response to the first data and a second driver configured to drive the first or second output node to the second level with a driving force different from that of the first driver in response to the second data, the second driver being turned off when the off signal is activated.

Abstract: Rejection of local oscillator harmonic response is provided in a mixing circuit with a pair of harmonic gating switches serially connected to the outputs of a balanced differential switching mixer and controlled by a gate clock signal having twice the frequency of a local oscillator signal controlling the switching mixer. An aperture or duty cycle of the gate clock signal determines which harmonic is rejected or suppressed, which is preferably a third and/or fifth harmonic since response of the balanced differential switching mixer to even harmonics is negligible. The resulting simple, efficient circuit is readily integrated directly into a phase-alternating mixer structure for a chopper-direct-conversion radio.

Abstract: A radio frequency (RF) demodulation circuit comprising: 1) a radio frequency (RF) mixer having a first input port capable of receiving an incoming RF signal having a frequency of RF and a second input port capable of receiving a first local oscillator (LO) signal having a frequency of LO, wherein the RF mixer generates a first intermediate frequency (IF) signal having a frequency of IF; 2) a frequency divider circuit capable of receiving the first LO signal having the frequency of LO and generating therefrom a second local oscillator (LO) signal having a frequency of LO/N and synchronized with the first LO signal; and 3) an intermediate frequency (IF) mixer having a first input port capable of receiving the first IF signal and a second input port capable of receiving the second LO signal having the frequency of LO/N, and wherein the IF mixer generates a baseband output signal.