Abstract: A digital-to-analog converter for converting a multiple bit digital input signal into multiple representative analog output signals includes a pulse density modulator, a logic controller, signal selection logic circuits and resistive-capacitive lowpass output filters. The pulse density modulator receives the N-M least significant bits of an N-bit digital input signal and in accordance therewith generates a pulse density modulated digital signal with a pulse density corresponding to a digital count of such N-M least significant bits. The logic controller receives the M most significant bits of the N-bit digital input signal and in accordance therewith generates multiple pairs of digital control signals. Each of the signal selection logic circuits receives the pulse density modulated digital signal and a respective pair of the digital control signals and in accordance therewith provides a respective one of a number of digital output signals.

Abstract: An electronic circuit suitable for sampling an incoming data bit stream in order to recover the information contained in the data stream contains an input section, a reference section, and a comparing section. The input section produces a ramp signal that switches between a first endpoint voltage and a second endpoint voltage in a periodic manner. The reference section furnishes a plurality of reference voltages between the two endpoint voltages. The comparing section compares the ramp signal to the reference voltages to produce corresponding sampling signals. Each sampling signal makes a first voltage transition as the ramp signal passes a corresponding reference voltage in going from the second endpoint voltage to the first endpoint voltage. Accordingly, the first transitions of the sampling signals occur in groups, each group being spread out in time during part of a period of the ramp signal. A data sampling portion of the circuit utilizes the sampling signals to sample the input data bit stream.

Abstract: A framing circuit, which frames bytes of data received from a serial data bit stream, prevents a short byte clock pulse from being formed when the byte clock signal, which identifies the beginning of each frame, is reset. The framing circuit utilizes a comparison stage to output a match signal each time an n-bit data bit pattern matches a programmable predetermined framing pattern, and to delay each n-bit pattern a delay time. The framing circuit also utilizes a counter to produce the byte clock signal, and a delay circuit to freeze the output of the counter for a predetermined delay time each time the match signal is output. The delay circuit also resets the byte clock signal so that the reset byte clock signal coincides with the output of the delayed data bit pattern. By freezing the output of the counter for a predetermined time, the width of the resulting pulse is lengthened.

Abstract: A phase-locked loop having a phase error processor (PEP) circuit in which a phase error is provided to the PEP circuit in the form of a first pulse stream comprising pulses of a width dictated by the phase error between the incoming data and a local clock and a second pulse stream comprising pulses of a reference width. The circuit includes two integrators having outputs coupled to first and second inputs of a comparator, respectively. Switches couple the first pulse stream to the input of one integrator and the second pulse stream to the input of the other integrator during a first time window and reverse the connections during a second time window. The switches are controlled by a SWAP signal which alternates state at regular intervals. The output of the comparator is exclusive-ORed with the SWAP signal in order to invert the comparator output signal every other window so as to average any input offset error of the comparator or offset due to mismatch of the integrators evenly between the two pulse streams.

Abstract: A jitter extraction circuit, which includes a cyclic phase differentiator, a control loop, and a jitter integrator, measures the jitter of a recovered clock signal formed from an incoming data bit stream. The phase differentiator differentiates a phase data word, which includes both a jitter component and a delta frequency component, to produce a differentiated phase data word. The control loop estimates and removes the delta frequency component to produce a filtered data word which primarily represents the jitter component. The jitter integrator recovers the original jitter component by integrating the filtered data word to produce a jitter data word. The jitter of the recovered clock signal is determined by the statistics of the jitter data words.

Abstract: A digital programmable loop filter for high frequency control systems applications utilizing a serial processing technique on pulse densities. The loop filter contains a proportional signal path and an integral signal path. A 4-time-slot sequencer time-multiplexes the serial proportional and integral signals to emulate a 1-pole/1-zero filter. An acquisition speed control circuit controls the acquisition time as well as step sizes of the scaler (proportional path) and the integrator (integral path) to provide loop variable programmability.

Abstract: A phase detector circuit, used in a very high frequency phase-locked loop, receives an incoming NRZI data stream and a phase-locked loop clock signal. For each data transition in the received data stream, the phase detector produces proportional phase error information in the form of two pulse signals PD1 and PD2. Pulse signal PD1 has a pulse width TW1 which corresponds to the amount and direction of any phase error between the data signal transition and the PLL clock signal. Pulse signal PD2 has a fixed width TW2 equal to half the period of the PLL clock signal. The phase detector also generates a recovered data signal and a recovered clock signal using identical parallel circuits so that the recovered signals are time synchronized. Furthermore, the recovered data signal is derived from signals in the phase error detection path, eliminating the need for two distinct circuits for data recovery and clock recovery.

Abstract: A digital testing system providing for cost efficient comprehensive testing of very high frequency phase-locked loop performance parameters. The system tests PLL performance parameters both at integrated circuit level and communication board level. Cost efficiency of the testing system allows for volume testing by manufacturers.

Abstract: A phase error processor interfaces a proportionate phase detector to a digital loop filter in a high frequency phase-locked loop (PLL). The PLL receives a high frequency stream of NRZI encoded data, which contains a variable density of data signal transitions. A phase detector in the PLL generates proportionate phase error information in the form of a phase error pulse signal PD1 and a reference pulse signal PD2 for each data transition in the incoming data s The phase error processor, using a "decimation" technique, integrates the proportionate phase error information from just one pair of adjacent positive and negative data transitions during each period of N clock cycles if the number of input data transitions which occur during that time period exceeds the expected minimum, otherwise the phase error processor passes no phase error information. The selection of window width is based on the coding scheme of the incoming data stream.

Abstract: A signed phase-to-frequency (`P-to-F`) converter for use in a very high frequency Phase Locked Loop is disclosed. The P-to-F converter receives an input signal indicating plus/minus phase errors and an enable signal. The input signal is converted into a count by a counting circuit. An upper part of the count signal is used to generate a 3-phase sawtooth digital pattern. A lower part of the count is converted by a lower-bit pulse density modulation (`PDM`) circuit to generate a signal indicating the binary weight of the lower part of the count. The output of the lower-bit PDM circuit is applied, along with the 3-phase digital pattern, to three higher-bit PDM circuits. The carry output of the higher-bit PDM circuits is the digital output of the P-to-F converter and is converted from a digital to an analog signal by RC filters. The positive and negative phase error is indicated by the leading/lagging phase among the 3-phase output waveforms.

Abstract: The present invention provides a modulator/generator circuit which includes the following features: a 1200 baud 4-phase differential phase shift keying (DPSK) modulator, a 300 baud frequency shift keying (FSK) modulator, a dual tone multi-frequency (DTMF) generator and 2100/2225 Hz answer tone generators. The DPSK modulator utilizes time-domain filtering techniques. It includes a spectrum controller that shapes the in-band frequency spectrum and attenuates the adjacent channel frequency components to eliminate the conventional requirement of band-pass filters after the modulator. The FSK modulator also utilizes a spectrum controller which, during each data transition, sends out six intermediate frequencies to smooth the frequency changeover. DTMF generation is accomplished by multiplexing two sine-wave counters into a DPSK sinewave look-up ROM.

Abstract: A phase-locked loop generates a periodic clock signal which matches the frequency of an input signal, such as digital data signals transmitted over an optical fiber. A ring oscillator or other clock generator generates a 2N-phase reference clock signal with a reference frequency f.sub.0, where N is a positive, odd integer having a value of at least three. The 2N reference clock phasor signals have evenly distributed phases. A waveform generator generates a 2N-phase control signal having a frequency .vertline.f.sub.M .vertline. which corresponds to the difference between the input signal's frequency and the reference frequency f.sub.0. The value of f.sub.M is greater than zero when the input signal's frequency is higher than f.sub.0, and it is less than zero when the input signal's frequency is less than f.sub.O. A frequency correction circuit (FCC) generates an output clock signal havng an output frequency which is equal to f.sub.0 +f.sub.M.

Abstract: A digital loop filter translates a multi-bit phase error input into a high resolution control signal utilizable as an advance-retard control for a multi-phase clock generator. The digital filter couples the multi-bit phase error input to the clock generator via a pulse density modulation (PDM) accumulator, providing multi-phase adjustment in a single sample clock cycle based on the overflow or underflow of the PDM accumulator. Variable PDM cycles are used to control loop filter bandwidth, permitting adjustable capture sequences. Thus, real proportional control of the multi-phase clock generator is limited only by the word size of the phase error input.

Abstract: An adaptive equalizer for compensating input signal frequency and phase distortion introduced in the input signal transmission media is provided. The adaptive equalizer includes frequency selection means for generating an output signal of a selected frequency in response to the input signal and a feedback signal. A comparator slices the equalizer output at predetermined levels. A controller receives the comparator output and provides a controller output representative of the voltage level of the comparator output. A digital filter receives the controller output and generates a corresponding binary signal as the feedback signal to the frequency selection means.

Abstract: A differential phase shift keying (DPSK) modulator utilizes time-domain filtering techniques. The DPSK modulator includes a data scrambler which receives a serial digital data input signal and generates an output signal representing the dibit value of the serial input sequence. The dibit signal is differentially encoded and then provided to a history generator which produces phase modulating vectors utilizing pulse density modulation (PDM). The carrier waveform is then modulated utilizing the modulating vectors to generate a DPSK output signal.

Abstract: A digital controlled clock provides ultra fine resolution for a sampling clock signal for recovering data from a received signal, the phase jump of the sampling clock signal being determined the number of stages in a multiphase clock generator that generates a number of equally-spaced phase clock outputs based on a reference clock signal. Phase selection is performed through a very low overhead phase commutator in response to phase advance/retard inputs. A clock deglitcher matched to the stages of the ring oscillator eliminates spikes generated when the phase commutator switches.

Abstract: A digital 2B1Q transmitter utilizes a dual modulator to generate a 2B1Q coded output by summing two binary modulated vectors in a 2:1 weighting ratio, allowing one modulating envelope generator to drive the dual modulator. The modulating envelope is coded in a 1-bit pulse density modulation (PDM) format, permitting the use of simple gating functions in performing the modulation function. The rising half of the transmit pulse is stored in the envelope generator, while the trailing half is derived from the rising half using the "1-x" function; this allows part of the summing functions to be reduced to OR gates.

Abstract: The present invention provides a timing recovery technique for baseband-coded data sequences which applies to line codes with inband timing information embedded in periodic signal transitions, such as zero-crossings. The technique utilizes a selection of data patterns, like mark-to-mark, which have zero-crossings at the "center" of a transition from a positive to negative mark. These so-called "bipolar patterns" consist of two polar-signals of opposite polarity sharing neighborly baud intervals. Because the random nature of a data sequence gives timing information a statistical behavior, a timing recovery system recovers a timing average, the efficiency of the system being given in terms of the timing variance. According to the present invention, a low variance estimate for the bipolar-pattern-center timing signal is obtained by proper filtering.

Abstract: An auto-threshold circuit in accordance with the present invention comprises a full-wave peak sensor for accurately estimating slice levels for input signal detection. The peak sensor is qualified such that the auto-threshold circuit does not track an input signal with no modulation. The input signal is windowed with a phase-locked-loop so that the peak sensor is coherent to the input signal, causing the circuit to be insensitive to noise spikes or input distortion outside the window. The auto-threshold circuit includes a digital loop filter which receives the output from an auto-threshold controller and generates a corresponding binary signal which is converted by a digital Sigma/delta modulator to a single bit pulse density modulated signal having a predetermined sampling frequency. An adaptive equalizer in accordance with the present invention shares the auto-threshold slicing signal for generating its error feedback signal.

Abstract: A quotient phase-shift processor is provided which includes novel techniques for realizing phase corrections of a digital phase-locked-loop. A binary phase-detector of the "early-late" type is combined with range-phase-detector circuitry to generate a variable lock acquisition speed. Phase measure and speed control are performed by incremental manipulation which feeds a novel "quotient" processor. The quotient processor integrates the incremental phase errors and performs phase corrections in a nonperiodic fashion, resulting in lower effective proportional loop gain than that provided in standard phase-locked-loops. Wide capture-range and low jitter are obtained by dynamically varying a loop time constant. Pattern dependent noise is reduced by a novel gating technique. High crystal-frequency requirements are reduced, extending the spectral application of digital phase-locked-loops.