Abstract: The present invention provides a digital frequency shift keying (FSK) demodulator circuit which receives a hard-limited FSK input signal and recovers the modulating baseband signal at 300 baud or less. The FSK demodulator includes a digital phase locked loop demodulator section which receives the FSK input signal and generates a pulse width modulated output the frequency of which is a function of the input signal frequency. The output of the PLL demodulator section is provided to a quantizer which generates a set of parallel numbers. A translating means, for example a code linearizer, converts the parallel numbers into corresponding parallel outputs which are representative of the frequency of the FSK input signal. The parallel outputs are processed by a digital filter which emulates a second-order, low-pass filter. The filter processes the parallel outputs utilizing pulse density modulation. A deglitcher removes noise from the filter output to provide the demodulated data output.

Abstract: In a receiver of the type that receives an incoming phase shift keying (PSK) signal and recovers data therefrom, a data recovery circuit which utilizes convolution techniques. The data recovery circuit generates an array of phase vectors representative of the incoming PSK signal and convolutes the vectors against a weighting curve to generate binary weighted outputs. The magnitude of the outputs represents one of the phases of the incoming PSK signal. If the incoming phase is undefined, the binary weighted outputs are not updated.

Abstract: A synchronizer circuit for recovering a clock signal from synchronizing strobes derived from a modulated dibit phase shift keying (PSK) input signal. A phase detector samples the output of a number controlled oscillator at synchronizing strobe intervals corresponding to zero crossings of the PSK input signal. The phase detector generates binary weighted outputs which are measured of the phase error between the number controlled oscillator and the synchronizing strobes.

Abstract: A digital PLL technique to provide an effective sampling interval and resolution shorter than the driver clock period. A multi-phase driver clock provides a clock signals phase-offset from each other. One clock output signal is used as the driver clock to clock an input sampler. A pattern of bit samples before, nominally at, and after a predicted clock edge indicates whether a leading or lagging phase should be substituted for the present driver clock signal. The phase difference is substantially less than the period of the fastest clock presently available to generate satisfactory shaped pulses.

Abstract: A technique for communicating digital data through a noisy medium using phase modulated carrier signals. A multiphase clock drives parallel channels to sample the received signal, avoiding the need for a phase locked loop. Data is recovered from the noisy carrier by a two stage statistical filtering technique and pattern analysis of the filtered signals.

Abstract: An interface circuit for converting a digital signal representing a dot-by-dot color video signal into a NTSC signal compatible with a television antenna input precompensates the digital for limitations in typical NTSC receivers. Various methods and circuits for precompensating the luminance amplitude, chrominance and chrominance amplitude content of the digital signal result in perceivably improved contrast and color purity.

Abstract: An interface circuit for converting a digital signal representing a dot-by-dot color video signal into a NTSC signal compatible with a television antenna input precompensates the digital for limitations in typical NTSC receivers. Various methods and circuits for precompensating the luminance amplitude, chrominance and chrominance amplitude content of the digital signal result in perceivably improved contrast and color purity.

Abstract: An interface circuit for converting a digital signal representing a dot-by-dot color video signal into a NTSC signal compatible with a television antenna input precompensates the digital for limitations in typical NTSC receivers. Various methods and circuits for precompensating the luminance amplitude, chrominance and chrominance amplitude content of the digital signal result in perceivably improved contrast and color purity.