Abstract: A DLL circuit for a semiconductor memory apparatus includes a delay line having a coarse delay chain, which has a plurality of coarse delayers connected in series and is inputted with a reference clock signal, and a plurality of fine delayers which receive output clock signals of the respective coarse delayers, and a delay control section for comparing phases of an output clock signal of a final coarse delayer among the coarse delayers with the reference clock signal and generating coarse control signals for controlling the coarse delayers and for comparing phases of an output clock signal of a fine delayer inputted with the output clock signals of the final coarse delayer, as a fine feedback clock signal, with the reference clock signal and generating fine control signals for controlling the fine delayers.

Abstract: Rejection of local oscillator alias response is provided in a mixing circuit by (1) a switching mixer producing an output that changes at least twice between two states (e.g., high-low-high or low-high-low) during each local oscillator period, and (2) a charge integrator integrating current output from the switching mixer over the local oscillator period. The switching mixer and charge integrator produce a sampled data format, double sideband signal with serial cancellation of the switching mixer's alias responses. An extension unit connected in series with the switching mixer and charge integrator, and implementing a transform function computing a difference between consecutive samples, produces a cascading effect with the switching mixer and charge integrator, optionally producing additional nulls suppressing alias response at frequencies near the local oscillator frequency.

Abstract: Rejection of local oscillator harmonic response is provided in a mixing circuit with a pair of harmonic gating switches serially connected to the outputs of a balanced differential switching mixer and controlled by a gate clock signal having twice the frequency of a local oscillator signal controlling the switching mixer. An aperture or duty cycle of the gate clock signal determines which harmonic is rejected or suppressed, which is preferably a third and/or fifth harmonic since response of the balanced differential switching mixer to even harmonics is negligible. The resulting simple, efficient circuit is readily integrated directly into a phase-alternating mixer structure for a chopper-direct-conversion radio.

Abstract: A phase alternating mixer is implemented by common-base differential transistor pairs, with two cross-coupled pairs providing a switching mixer function with harmonic gating suppression of harmonic responses to the switching mixing by control of local oscillator signals controlling switching of the differential transistor pairs. Rather than a resistive load, a switched capacitance load and integrating capacitors are connected to the output of the differential transistor pairs to provide first order low pass filtering of the double sideband output from the differential pairs, with a controlled bandwidth. Channel select switches demultiplex the double sideband signal into a baseband signal.

Abstract: An analog-to-digital converter error detector suitable for single-chip control loop applications employs a single comparator determining the difference between an initial input voltage and a reference voltage in one or more conversion iterations, with the difference reduced in nonlinear steps during each conversion iteration based on the ratio between sampling and discharge capacitances. The number of conversion iterations required to reduce the initial input voltage to below the reference voltage is counted as representing the difference, with output codes representing the conversion iteration count having a step size increasing with the count value and selected to reduce downstream processing.

Abstract: Dithering for the output of a digital pulse width modulator is provided by a pulse-density modulator formed from an adder incrementing a pulse-density count and generating a carry signal latched to a plus-one generator, which in turn adds a phase-division period to each of one or more selected pulses within a predetermined series of pulses from the digital pulse width modulator. Selected pulses are advanced by triggering a leading edge of the pulse at a time one phase-division period before the system clock edge, allowing trailing edges to be extended and providing minimal latency delay.

Abstract: A radio frequency (RF) receiver comprising: 1) a local oscillator (LO) circuit capable of receiving a local oscillator (LO) reference signal having frequency, LO, and a double sideband (DSB) clock signal having a frequency, DSB, and generating therefrom an in-phase product signal of the LO reference signal and the DSB clock signal in which a polarity of the LO reference signal is reversed at the DSB frequency of the DSB clock signal; and 2) a first radio frequency (RF) mixer having a first input port capable of receiving the in-phase product signal from the LO circuit and a second input port capable of receiving a modulated radio frequency (RF) signal, wherein the first RF mixer generates a first downconverted output signal.

Abstract: An edge counter counting both rising and falling edges of an input signal is implemented with combinational logic, without using flip-flops. The combinational logic is designed using intermediate signals and state transitions producing an output signal having a cycle corresponding to a predetermined odd or even number of input signal edges, with the logic optimized and protected against entry into “stuck” states. A low power, low gate count edge counter is thus implemented with an output signal duty cycle at least as balanced as the input counter duty cycle.

Abstract: A chopper-direct-conversion (CDC) radio receiver includes a phase-alternating mixer receiving an antenna input signal and at least one local oscillator signal and generating a double sideband signal in a single mixing step. The phase-alternating mixer may be implemented by two parallel mixers each mixing the input signal with one of two local oscillator signals and an adder receiving and summing outputs from the two parallel mixers, by a track-and-hold circuit sampling the input signal based upon the local oscillator signal, or by a window averaging circuit averaging the input signal across a period of the local oscillator signal. The CDC architecture is suitable for fabrication on a single chip and offers solutions to virtually all problems found in conventional direct-conversion receivers.

Abstract: A radio frequency (RF) demodulation circuit comprising a harmonic rejection mixing stage capable of receiving and mixing an incoming radio frequency (RF) signal having a frequency RF and a reference local oscillator (LO) signal having a frequency LO and generating an output signal in which out-of-band harmonic signals are suppressed. The harmonic rejection mixing stage comprises 1) a multiphase local oscillator (LO) generator for receiving the reference LO signal and generating M phase-shifted local oscillator signals having frequencies LO and 2) M mixers, each of the M mixers receiving the incoming radio frequency signal and one of the M phase-shifted local oscillator signals. Each of the M mixers generates a subcomponent signal. The subcomponent signals are then scaled and combined to produce the output signal.

Abstract: An interbody spinal device for insertion into an intervertebral disc space of a vertebrate animal, where the device is adapted to rotate within the intervertebral disc space upon insertion. The invention also provides a method of distracting and/or maintaining two adjacent vertebrae of a vertebrate animal until the two adjoining vertebrae are fused, the method comprising: (a) creating an intervertebral disc space between the two adjacent vertebrae through an aperture; and (b) inserting an interbody spinal device through an aperture into the intervertebral disc space.

Abstract: A RF down/up-conversion circuit comprising: 1) a local oscillator chopping circuit comprising: a) a frequency divider circuit for receiving a first local oscillator (LO) signal having a frequency of LO and generating a frequency-divided second local oscillator (LO) signal having a frequency of LO/N and synchronized with the first LO signal; and b) a multiplier for receiving the first and second LO signals and generating a product signal of the first and second LO signals; and 2) a differential radio frequency (RF) mixer having a first differential input port for receiving the product signal from the multiplier and a second differential input port for receiving a first differential modulated radio frequency (RF) signal and a second differential modulated radio frequency (RF) signal, wherein the differential RF mixer generates a differential output signal.

Abstract: A radio frequency (RF) demodulation circuit comprising: 1) a radio frequency (RF) mixer having a first input port capable of receiving an incoming RF signal having a frequency of RF and a second input port capable of receiving a first local oscillator (LO) signal having a frequency of LO, wherein the RF mixer generates a first intermediate frequency (IF) signal having a frequency of IF; 2) a frequency divider circuit capable of receiving the first LO signal having the frequency of LO and generating therefrom a second local oscillator (LO) signal having a frequency of LO/N and synchronized with the first LO signal; and 3) an intermediate frequency (IF) mixer having a first input port capable of receiving the first IF signal and a second input port capable of receiving the second LO signal having the frequency of LO/N, and wherein the IF mixer generates a baseband output signal.

Abstract: Disclosed is a video data re-clocking scheme for use in highly integrated system circuits to overcome the problem of beat patterns. These type of circuits contain many subsystem blocks, and each of those blocks may use different clock frequencies. Due to implementation constraints, clock interferences from nearby blocks are unavoidable. In a video display sub-system, these interferences produce beat patterns that substantially degrade video quality. One disclosed embodiment of the invention employs re-clocking flips-flops to re-time the input signals feeding the video Red/Green/Blue Digital-to-Analog converters (RGB DACs) such that data edge jitters due to interference are removed. The resulting picture quality is free of beat patterns.

Abstract: There is disclosed a radio frequency (RF) demodulation circuit comprising: 1) a first RF mixer having a first input port for receiving an in-phase RF signal having a frequency of RF and a second input port for receiving an in-phase local oscillator (LO) signal having a frequency of LO, wherein LO is approximately equal to one-half of RF, and wherein the first RF mixer generates a first intermediate frequency (IF) signal having a frequency of LO; 2) a second RF mixer having a first input port for receiving an out-of-phase RF signal having a frequency of RF and a second input port for receiving an out-of-phase local oscillator (LO) signal having a frequency of LO, and wherein the second RF mixer generates a second intermediate frequency (IF) signal having a frequency of LO; and 3) a first signal combiner for combining the first and second IF signals to generate a composite IF signal, wherein the first signal combiner combines a first leakage signal from the first RF mixer and a second leakage signal from the se

Abstract: A method and apparatus are directed to improving the response of a phase-locked loop (PLL) by reducing the jitter transfer characteristics. A new PLL system, referred to as an IS-PLL, includes an integrator and stability filter that are arranged to provide improved low frequency and high frequency performance while maintaining reduced jitter. The design of the IS-PLL is accomplished using superposition such that the integrator and stability filter designs are simplified. Design coefficients are chosen such that the system transfer function has a high frequency roll-off that is equivalent to a second order low-pass filter. Other design coefficients are chosen such that the system transfer function provides for improved DC tracking and reduced jitter when tracking peaks in an error signal. The IS-PLL has a third order system transfer function that can be realized with simplified design criteria.

Abstract: A multi-dimensional differential signaling (MDDS) system is provided. A current loop is formed between N different communication lines and a corresponding differential is produced by loads coupled between the communication lines. The MDDS system may be two-dimensional or multi-dimensional. The number of communications lines chosen for the MDDS system affects the number of differential pairs in the system as well as the bits of information that may be transmitted. More than two states are provided by the MDDS system. For example, if three communication lines are used within the system, six states are provided. A star or delta load is used to produce the differential across the communication lines.

Abstract: A trapezoidal waveform synthesizer converts a digital phase error signal into a plurality of phase-separated trapezoidal analog waveforms. The trapezoidal waveform synthesizer includes an up/down counter that counts the positive and negative phase errors and generates a multi-bit, parallel digital counter output signal that indicates a cumulative current value of the phase errors. The counter output signal includes a least significant bit (LSB) portion and a most significant bit (MSB) portion. An upper PDM circuit converts the MSB portion of the output signal counter and a portion of the LSB portion of the counter output signal to a plurality of sets of serially-weighted multi-bit output signals. A lower PDM circuit converts the MSB and LSB portions of the counter output signal to a plurality of serially-weighted single-bit output signals.

Abstract: A high speed data receiver for recovering binary or MLT3 encoded data which has been received via a cable. An adaptive equalizer provides signal gain which increases with frequency and adapts according to the length of the cable. Control over such adaptive equalizing is achieved by monitoring the peak-to-peak amplitude, amplitude peaks and differences between amplitude peaks of the equalized data signal during defined time intervals. Baseline restoration and dynamic data slicing are also provided.

Abstract: An adaptive equalizer for adaptively equalizing a data signal received via a communications path having a signal loss magnitude which increases with signal frequency includes multiple, serially coupled adaptive filter stages. The input data signal is successively filtered and magnitude weighted by successive adaptive filter circuits in accordance with corresponding, respective adaptation control signals. The frequency domain ratio of output signals to corresponding input signals for each adaptive filter circuit represents a corresponding, respective adaptive filter transfer function. An equalizer controller, in accordance with a single equalization control signal, generates the multiple, individual adaptation control signals.