Abstract: An integrated circuit includes an input terminal for applying an input signal, a further input terminal for applying a further input signal having a level differing from the level of the initial input signal, an output terminal for providing an output signal, a switching unit having a controllable switch, which is arranged between the input terminal and the output terminal, and a further switching unit, which is arranged between the further input terminal and the output terminal. The integrated circuit is operated in a first and subsequent second operating state. The controllable switch of the switching unit is controlled to be conductive in the first and second operating state. In the first operating state, the output signal is provided in dependence on the level of the input signal, and in the second operating state in dependence on the level of the second input signal.

Abstract: A semiconductor memory having read amplifier strips having a plurality of read amplifiers and having memory cell fields which have a plurality of memory cells connected to bit lines is disclosed. The read amplifier strips include at least two outer read amplifier strips between which the remaining read amplifier strips and the memory cell fields are arranged, wherein adjacent to at least one of the outer read amplifier strips, a reference circuit field is arranged, which has reference lines and reference circuit elements connected thereto, and wherein the reference lines are shorter than the bit lines of the memory cell fields.

Abstract: A memory circuit includes a plurality of bit lines and a plurality of memory cells which may be written to via a respective bit line. The memory circuit further includes a bit line control circuit. The bit line control circuit is configured to write, in a bit line-selective manner, a weak value to a memory cell coupled to a bit line selected.

Abstract: A description is given of a method for charge reversal of a circuit part of an integrated circuit from a first electrical potential to a second electrical potential of a first voltage network. In this case, the circuit part is connected to the first voltage network for charge reversal. Furthermore, the circuit part is connected to a second voltage network for charge reversal, said second voltage network providing a third electrical potential between the first and the second electrical potential. The circuit part is automatically isolated from the second voltage network before its electrical potential reaches the second electrical potential.

Abstract: PTH compounds having PTH-like activity and comprising at least one modification, said modification being either 1. at least one radical selected from a L- or D-?-amino acid, C2-6alcoxycarbonyl and optionally substituted C1-8alkyl, C2-8alkenyl, C2-8alkynyl, aralkyl, aralkenyl or C3-6cycloalkyl-C1-4alkyl and attached to the terminal amino group of the PTH compound, and/or at least one radical selected from C2-6alcoxycarbonyl and optionally substituted C1-8alkyl, C2-8alkenyl, C2-8alkynyl, aralkyl, aralkenyl or C3-6cycloalkyl-C1-4alkyl and attached to one or more side chain amino groups of the PTH compound, or 2.

Abstract: An arrangement of signal line pairs and amplifiers is disclosed. One embodiment provides each signal line pair of a group of signal line pairs that are directly adjacent and run parallel to one another is respectively assigned an amplifier from a group of amplifiers arranged successively in a signal line direction. Each signal line pair includes a first and a second signal line, between which the amplifier assigned to the respective signal line pair is arranged. The position of an amplifier is assigned to a specific signal line pair in the amplifier group along the signal line direction is chosen in such a way that a first coupling section which forms the first signal line assigned to the respective amplifier together with its adjacent lines along the amplifier group, and a second coupling section, which forms the second signal line assigned to the respective amplifier together with its adjacent lines along the amplifier group, substantially have the same coupling properties.

Abstract: A method and a device for regulating the threshold voltage of a transistor is disclosed. The device includes a circuit configured for modifying a voltage applied at a bulk connection of the transistor such that the threshold voltage of the transistor is substantially temperature-independent at least in a first temperature range. In one embodiment, the device includes a memory device, and the transistor is a transistor of a sense amplifier of the memory device.

Abstract: An integrated circuit with buried control line structures. In one embodiment, the control lines are subdivided into sections, wherein regions free of switching transistors are provided at intervals along the control lines. Connections for feeding the control potentials into the sections of the control lines are provided at least in a subset of the regions free of switching transistors. The isolations lines are connected to one another by an interconnect running transversely with respect to the control lines.

Abstract: A semiconductor memory device and method with a changeable substrate potential. One embodiment provides for operating a semiconductor memory device having at least one read or write/sense amplifier. The method includes changing the substrate potential of the read or write/sense amplifier.

Abstract: A memory component comprises a plurality of bit lines, on which memory cells are arranged, and a plurality of sense amplifiers, which are arranged in a row, each sense amplifier being connected to two bit lines. A bit line which is connected to a first sense amplifier in the row is arranged directly adjacent to a bit line which is connected to a second sense amplifier in the same row.

Abstract: A semiconductor integrated circuit device and method for reducing gate induced leakage current associated with circuits of the semiconductor electrical device, such as a semiconductor integrated circuit memory device. During a standby mode, a voltage supplied to a plurality of circuits is reduced so as to reduce gate induced leakage (GIDL) current associated with said plurality of circuits. During time intervals while in the standby mode, the voltage supplied to a subset of said plurality of circuits is increased to a level necessary for a refresh function associated with said subset of said plurality of circuits and then it is reduced upon completion of said refresh function. In the example a semiconductor memory device, the circuits that are manipulated in this manner are wordline driver circuits.

Abstract: An apparatus and method for operating a sense amplifier connecting/disconnecting circuit arrangement, in particular for a semiconductor memory device, including a switching device for connecting/disconnecting a sense amplifier to/from a bit line of a first cell field region, and for connecting/disconnecting the sense amplifier to/from from a bit line of a second cell field region, as a function of the state of control signals applied at control lines. Driver devices drive the control signal. Additional switches change the state of the control signals.

Abstract: A claw pole stator for a stepping motor having at least a first and a second claw pole plate, each of which has a yoke and pole claws, the first and the second claw pole plate having the same number of pole claws and pole gaps and being coaxially disposed with respect to one another, wherein the pole claws of the first claw pole plate engage in the pole gaps of the second claw pole plate, and having a toroid coil that is located between the first claw pole plate and the second claw pole plate and at least the pole claws of the first claw pole plate being divided into several sections that comprise a first section that is connected to the yoke and is substantially trapezoidal in shape and tapered, narrowing with increasing distance from the yoke and that comprise a second section that adjoins the first section and is substantially rectangular in shape.

Abstract: A memory contains memory cells and is clock-controlled on the basis of a basic clock signal at the frequency fc, wherein a chosen memory cell is accessed by closing an addressed column selection switch. The memory has a pulse generator to produce a column selection pulse which closes the addressed column selection switch, wherein the pulse generator contains a first pulse timer for prescribing a fixed time Tf for the length Txof the column selection pulse and a second pulse timer for prescribing a frequency-dependent time Tv, which is proportional to the clock signal period Tc=1/fc, for the length of the column selection pulse.

Abstract: The invention relates to a compensation cylinder unit that acts as a drive for the electrode arms of a welding device. The unit comprises a cylinder and at least two pressure chambers, which are sub-divided by a piston assembly and which can be alternately supplied with a pressurized medium by means of a valve assembly for controlling the drive displacement. According to the invention, the valve assembly comprises a proportional valve which can be controlled by a control unit, first in accordance with harmonized path signals that represent the position of the piston assembly and then by pressure signals that respectively represent the pressure in the pressure chambers, in such a way that the difference between the pressures that prevail in the pressure chambers in a predeterminable position of the piston assembly assumes a constant value that represents the weight compensation force of at least one electrode arm.

Abstract: The invention relates to a device for the insulation of the stator slots of an electric machine that has a stator having a plurality of stator poles and stator slots located between the stator poles, comprising an insulating body that has moldings adapted to the shape of the stator slots and can be slid onto the stator in an axial direction, and a cover piece that can be connected to an end face of the insulating body, in order after the windings have been applied to the insulating body, to carry the windings (36) at the end face of the stator and to cover them.

Abstract: An integrated circuit comprises a bit line pair having two bit lines, a sense amplifier having at least one transistor, the sense amplifier amplifying a charge difference between the bit lines of the bit line pair; and a control unit connected to a substrate terminal of the at least one transistor, the control unit applying a substrate potential dependent on an operating state of the integrated circuit to the substrate of the at least one transistor.

Abstract: A semiconductor integrated circuit device and method for reducing gate induced leakage current associated with circuits of the semiconductor electrical device, such as a semiconductor integrated circuit memory device. During a standby mode, a voltage supplied to a plurality of circuits is reduced so as to reduce gate induced leakage (GIDL) current associated with said plurality of circuits. During time intervals while in the standby mode, the voltage supplied to a subset of said plurality of circuits is increased to a level necessary for a refresh function associated with said subset of said plurality of circuits and then it is reduced upon completion of said refresh function. In the example a semiconductor memory device, the circuits that are manipulated in this manner are wordline driver circuits.

Abstract: A semiconductor memory having at least one memory cell adapted to store a data value, and adapted to be connected to a data line through a switch device controlled by a control signal. The invention also relates to a tri-state driver device for driving the control signal. Further, there is a method for operating a memory, in which the memory has a memory cell adapted to store a data value, and adapted to be connected to a data line through a switch device controlled by a control signal.

Abstract: The present invention relates to methods for repairing memory chips (7) with redundant cell areas and fuses using microlithography means, characterized by the following method steps: a) photoresist is applied to at least one wafer (6) which is to be repaired; b) a mask (1) is created in line with the chip-specific fuse coordinates; and c) at least one wafer (6) provided with photoresist is exposed using an exposure means through the mask (1); and an arrangement for a method for repairing memory chips (7) with redundant cell areas and fuses using microlithography means, where the arrangement comprises an application unit for photoresist onto wafers (6) which are to be repaired, a controllable mask (1) and an exposure means (2).