Abstract: A method and a device for regulating the threshold voltage of a transistor is disclosed. The device includes a circuit configured for modifying a voltage applied at a bulk connection of the transistor such that the threshold voltage of the transistor is substantially temperature-independent at least in a first temperature range. In one embodiment, the device includes a memory device, and the transistor is a transistor of a sense amplifier of the memory device.

Abstract: The invention relates to a device for the insulation of the stator slots of an electric machine that has a stator having a plurality of stator poles and stator slots located between the stator poles, comprising an insulating body that has moldings adapted to the shape of the stator slots and can be slid onto the stator in an axial direction, and a cover piece that can be connected to an end face of the insulating body, in order after the windings have been applied to the insulating body, to carry the windings (36) at the end face of the stator and to cover them.

Abstract: An electronic component has a first bit line and a second bit line, which are coupled to a plurality of memory cells, a line for providing a precharging potential, a resistance component which is connected to the line, a first switch which is coupled between the resistance component and the first bit line for connection of the first bit line to the resistance component, and a second switch, which is coupled between the resistance component and the second bit line, for connection of the second bit line to the resistance component. The electrical resistance of the resistance component is controllable in order to assume a predetermined first resistance value or a predetermined second resistance value which is higher than the first resistance value.

Abstract: An integrated semiconductor memory includes a sense amplifier with a first subamplifier for driving memory cells of a first memory cell array and a second subamplifier for driving memory cells of a second memory cell array. The subamplifiers are connected via continuous lines to bit lines of the first memory cell array and to bit lines of the second memory cell array. The subamplifiers can be operated by applying a single control signal (MUXl, MUXr) in a first operating state for reading in, reading out, and refreshing information of the memory cells and in a second operating state for precharging the bit lines. Reduction of the signal line due to losses is avoided as a result of direct coupling the subamplifiers to the respective memory cell arrays.

Abstract: A fuel cell system has a fuel cell unit including an anode, and a recirculation unit for recirculating hydrogenous operating material flowing out of the fuel cell unit back into the fuel cell unit, wherein the recirculation unit has at least one drive unit for driving a flow of an operating material, and the drive unit is configured as a pneumatic drive unit or hydraulic drive unit for utilizing an energy of a fluid.

Abstract: In a method and an apparatus for printing on material in web form print images are successively applied to the web by a transfer cylinder. The web is continuously drawn into the printing station and the speed at which the web is moved in the printing station during a printing operation is greater than the speed at which it is drawn into the printing station. After the printing operation the web is positioned in the printing station for the following printing operation relative to the transfer cylinder which is not in contact with the web during a part of a revolution of 360.degree., and at the same time the path of the web is altered in accordance with the change in the speed thereof. The web is driven by the impression cylinder which is associated with the transfer cylinder and around the peripheral surface of which the web partially passes. Positioning of the web for the respectively following printing operation is implemented by a change in the rotary movement of the impression cylinder.

Abstract: A memory component comprises a plurality of bit lines, on which memory cells are arranged, and a plurality of sense amplifiers, which are arranged in a row, each sense amplifier being connected to two bit lines. A bit line which is connected to a first sense amplifier in the row is arranged directly adjacent to a bit line which is connected to a second sense amplifier in the same row.

Abstract: The invention relates to semiconductor memories, and in particular, to DRAMs with a memory subunit including a memory cell in which a data value is stored and which is adapted to be connected with a bit line to which a complementary bit line is assigned, and a precharge/equalize circuit assigned to the memory cell, the precharge/equalize circuit serving to charge, prior to the reading out of the memory cell, the bit line and the complementary bit line in the region of the memory cell to the same voltage level, and being switched off during the reading out of the memory cell. The semiconductor memory in addition has a control circuit connected with the precharge/equalize circuit for switching on and off the precharge/equalize circuit.

Abstract: A method for fabricating a semiconductor gate structure including depositing at least one sacrificial layer on a semiconductor substrate; patterning the at least one sacrificial layer to form at least one cutout in the at least one sacrificial layer for uncovering the semiconductor substrate; forming a sidewall spacer over the sidewalls of the at least one sacrificial layer in the at least one cutout; forming a gate dielectric on the semiconductor substrate in the cutout; providing a gate electrode in the at least one cutout in the at lest one sacrificial layer; and removing the at least one sacrificial layer for the uncovering the gate electrode surrounded by the sidewall spacer. A semiconductor device is also provided.

Abstract: The invention relates to semiconductor memories and in particular to DRAMs. A semiconductor memory is provided comprising at least one memory cell adapted to store a data value, and adapted to be connected to a data line through a switch device controlled by a control signal, further comprising a tri-state driver device for driving the control signal. Further, a method for operating a memory is provided, the memory comprising a memory cell adapted to store a data value, and adapted to be connected to a data line through a switch device controlled by a control signal, the method comprising the steps: driving the control signal at a first voltage level when a read operation is to be performed; and driving the control signal at a second voltage level different from the first voltage level when a write operation is to be performed. Advantageously, the first voltage level used for the read operation is lower than the second voltage level used for the write operation.

Abstract: In a method and an apparatus for printing on material in web form print images are successively applied to the web by a transfer cylinder. The web is continuously drawn into the printing station and the speed at which the web is moved in the printing station during a printing operation is greater than the speed at which it is drawn into the printing station. After the printing operation the web is positioned in the printing station for the following printing operation relative to the transfer cylinder which is not in contact with the web during a part of a revolution of 360°, and at the same time the path of the web is altered in accordance with the change in the speed thereof. The web is driven by the impression cylinder which is associated with the transfer cylinder and around the peripheral surface of which the web partially passes. Positioning of the web for the respectively following printing operation is implemented by a change in the rotary movement of the impression cylinder.

Abstract: A field-effect transistor includes a semiconductor substrate, a source region formed in the semiconductor substrate, a drain region formed in the semiconductor substrate, a channel region formed in the semiconductor substrate, wherein the source region is connected to a source terminal electrode and the drain region is connected to a drain terminal electrode, wherein the channel region comprises a first narrow width channel region and a second narrow width channel region connected in parallel regarding the source terminal electrode and the drain terminal electrode, and wherein the first narrow width channel region and/or the second narrow width channel region comprise lateral edges narrowing the width of the narrow width channel region is such a way that a channel formation in the narrow width channel region is influenced by a mutually influencing effect of the lateral edges, and a gate electrode arranged above the first and second narrow width channel regions.

Abstract: A semiconductor circuit has at least one generator fuse for setting a supply voltage and at least one redundancy fuse for activating a redundancy element. A first read-out device is provided for reading out the generator fuse and a second read-out device reads out the redundancy fuse. The first read-out device is configured to read out the generator fuse at a first instant, and the second read-out device is configured to read out the redundancy fuse at a second instant.

Abstract: An integrated semiconductor memory includes a sense amplifier with a first subamplifier for driving memory cells of a first memory cell array and a second subamplifier for driving memory cells of a second memory cell array. The subamplifiers are connected via continuous lines to bit lines of the first memory cell array and to bit lines of the second memory cell array. The subamplifiers can be operated by applying a single control signal (MUX1, MUXr) in a first operating state for reading in, reading out, and refreshing information of the memory cells and in a second operating state for precharging the bit lines. Reduction of the signal line due to losses is avoided as a result of direct coupling the subamplifiers to the respective memory cell arrays.

Abstract: A voltage level converter device for the conversion of an input signal, which is at a first voltage level, into an output signal, which is at a second voltage level that differs from the first voltage level, where the voltage level converter device has at least one transistor, and in which an additional transistor, controlled by a control signal at a voltage level corresponding to that of the input signal, is provided in a current path that is to be accordingly switched on or off when the output signal switches over for switching that path on or off.

Abstract: The invention relates to a method for operating a sense amplifier connecting/disconnecting circuit arrangement, and to a sense amplifier connecting/disconnecting circuit arrangement, in particular for a semiconductor memory device, including a switching device for connecting a sense amplifier device to a bit line or to a cell field region, respectively, and for disconnecting the sense amplifier device from the bit line or from the cell field region, respectively, as a function of the state of a control signal applied at a control line; a driver device for driving the control signal, wherein an additional device, in particular an additional switch is provided, by means of which a change of state of the control signal applied at the control line can be effected.

Abstract: The invention relates to semiconductor memories, and in particular, to DRAMs with a memory subunit including a memory cell in which a data value is stored and which is adapted to be connected with a bit line to which a complementary bit line is assigned, and a precharge/equalize circuit assigned to the memory cell, the precharge/equalize circuit serving to charge, prior to the reading out of the memory cell, the bit line and the complementary bit line in the region of the memory cell to the same voltage level, and being switched off during the reading out of the memory cell. The semiconductor memory in addition has a control circuit connected with the precharge/equalize circuit for switching on and off the precharge/equalize circuit.

Abstract: PTH compounds having PTH-like activity and comprising at least one modification, said modification being either 1. at least one radical selected from a L- or D-?-amino acid, C2-6alcoxycarbonyl and optionally substituted C1-8alkyl, C2-8alkenyl, C2-8alkynyl, aralkyl, aralkenyl or C3-6cycloalkyl-C1-4alkyl and attached to the terminal amino group of the PTH compound, and/or at least one radical selected from C2-6alcoxycarbonyl and optionally substituted C1-8alkyl, C2-8alkenyl, C2-8alkynyl, aralkyl, aralkenyl or C3-6cycloalkyl-C1-4alkyl and attached to one or more side chain amino groups of the PTH compound, or 2.

Abstract: A method for fabricating a semiconductor gate structure including depositing at least one sacrificial layer on a semiconductor substrate; patterning the at least one sacrificial layer to form at least one cutout in the at least one sacrificial layer for uncovering the semiconductor substrate; forming a sidewall spacer over the sidewalls of the at least one sacrificial layer in the at least one cutout; forming a gate dielectric on the semiconductor substrate in the cutout; providing a gate electrode in the at least one cutout in the at lest one sacrificial layer; and removing the at least one sacrificial layer for the uncovering the gate electrode surrounded by the sidewall spacer. A semiconductor device is also provided.

Abstract: A voltage level converter device for the conversion of an input signal, which is at a first voltage level, into an output signal, which is at a second voltage level that differs from the first voltage level, where the voltage level converter device has at least one transistor, and in which an additional transistor, controlled by a control signal at a voltage level corresponding to that of the input signal, is provided in a current path that is to be accordingly switched on or off when the output signal switches over for switching that path on or off.