Patents by Inventor Hideaki Kawahara

Hideaki Kawahara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10323717
    Abstract: In a friction transmission belt including a rubber layer forming a pulley contact surface, the rubber layer includes a rubber composition containing hydrophilic inorganic filler and a sliding-resistant material. The sliding-resistant material protrudes from the pulley contact surface, and is at least one of hydrophobic resin particles and hydrophobic resin fibers having an official regain of 0.4% or below, and in the rubber composition, a content of the hydrophilic inorganic filler with respect to 100 parts by mass of the rubber component is 35 parts by mass or more.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: June 18, 2019
    Assignee: BANDO CHEMICAL INDUSTRIES, LTD.
    Inventors: Takayuki Okubo, Shinji Takahashi, Hideaki Kawahara
  • Patent number: 10309487
    Abstract: In a friction transmission belt including a rubber layer forming a pulley contact surface, the rubber layer includes a rubber composition containing polyolefin particles and an inorganic filler. In the rubber composition, a total content of the polyolefin particles and the inorganic filler with respect to 100 parts by mass of a rubber component is 85 parts by mass or more.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: June 4, 2019
    Assignee: BANDO CHEMICAL INDUSTRIES, LTD.
    Inventors: Takayuki Okubo, Shinji Takahashi, Hideaki Kawahara
  • Patent number: 10290699
    Abstract: An integrated trench capacitor and method for making the trench capacitor is disclosed. The method includes forming a trench in a silicon layer, forming a first dielectric on the exposed surface of the trench, performing an anisotropic etch of the first dielectric to expose silicon at the bottom of the trench, implanting a dopant into exposed silicon at the bottom of the trench, forming a first polysilicon layer over the first dielectric, forming a second dielectric over the first polysilicon layer, and forming a second polysilicon layer over the second dielectric to fill the trench.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: May 14, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hideaki Kawahara, Binghua Hu, Sameer Pendharkar
  • Patent number: 10256337
    Abstract: A device includes a transistor formed on a substrate. The transistor includes an n-type drain contact layer, an n-type drain layer, an oxide layer, a p-type body region, a p-type terminal region, body trenches, and terminal trenches. The n-type drain contact layer is near a bottom surface of the substrate. The n-type drain layer is positioned on the n-type drain contact layer. The oxide layer circumscribes a transistor region. The p-type body region is positioned within the transistor region. The p-type terminal region extends from under the oxide layer to an edge of the transistor region, thereby forming a contiguous junction with the p-type body region. The body trenches is within the transistor region and interleaves with the p-type body region, whereas the terminal trenches is outside the transistor region and interleaves with the p-type terminal region.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: April 9, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hideaki Kawahara, Christopher Boguslaw Kocon, Seetharaman Sridhar, Simon John Molloy, Satoshi Suzuki
  • Publication number: 20190051721
    Abstract: Embodiments of a deep trench capacitor are disclosed. In one example a plurality of deep trenches is located in a first region of a semiconductor wafer, the first region having a first conductivity type. A corresponding dielectric layer is located on a surface of each of the plurality of deep trenches, and a corresponding doped polysilicon filler is located within each of the dielectric layers. Dielectric-filled trenches are located between each of the dielectric layers and the surface of the semiconductor wafer.
    Type: Application
    Filed: October 18, 2018
    Publication date: February 14, 2019
    Inventors: Binghua Hu, Hideaki Kawahara, Sameer P. Pendharkar
  • Publication number: 20190030844
    Abstract: A shaped structure and a fabric material are set in a belt mold such that the shaped structure and the fabric material are respectively positioned inside and outside with respect to each other. While each of compression layer-forming portions comprised of ridges of the shaped structure covered with the fabric material is fitted in an associated one of compression layer-shaping grooves of the belt mold, the shaped structure is pressed toward the belt mold and heated to be crosslinked, and integrated with the fabric material, thereby molding a cylindrical belt slab. The belt slab is cut into ring-shaped pieces having two or more of the compression layer-forming portions.
    Type: Application
    Filed: September 28, 2018
    Publication date: January 31, 2019
    Applicant: BANDO CHEMICAL INDUSTRIES, LTD.
    Inventors: Naohisa HARUSHIGE, Kouichi TSUJINO, Tomoaki HATA, Hideaki KAWAHARA, Hisashi IZUMI, Yohei HATTORI, Koichi HOSOKAWA
  • Publication number: 20190022963
    Abstract: A production method of a raw edge V-belt uses a belt mold having a plurality of compressed rubber layer-shape grooves arranged adjacent to one another. A shaped structure having a plurality of compressed rubber layer-forming portions on an outer peripheral surface is crosslinked to form a belt slab, while the compressed rubber layer-forming portions fitted in the respective compressed rubber layer-shape grooves of the belt mold. The belt slab is cut into ring-shaped pieces such that one ring-shaped piece corresponds to one compressed rubber layer-forming portion.
    Type: Application
    Filed: September 21, 2018
    Publication date: January 24, 2019
    Applicant: BANDO CHEMICAL INDUSTRIES, LTD.
    Inventors: Naohisa HARUSHIGE, Tomoaki HATA, Yusaku TAOSHITA, Hideaki KAWAHARA, Masaki MIYANISHI, Yohei HATTORI, Hirokazu SAKURAI
  • Publication number: 20190022964
    Abstract: A production method of a V-belt uses a belt mold having a plurality of compression layer-shape grooves arranged adjacent to one another in a groove width direction. A shaped structure having a plurality of ridges on an outer peripheral surface is crosslinked and combined with a fabric material to form a belt slab, while the compression layer-forming portions, which are the ridges covered with the fabric material, being fitted in the respective compression layer-shape grooves of the belt mold. The belt slab is cut into ring-shaped pieces such that one ring-shaped piece corresponds to one compression layer-forming portion.
    Type: Application
    Filed: September 21, 2018
    Publication date: January 24, 2019
    Applicant: BANDO CHEMICAL INDUSTRIES, LTD.
    Inventors: Yohei HATTORI, Tomoaki HATA, Hirokazu SAKURAI, Takashi MATSUOKA, Hideaki KAWAHARA, Hisashi IZUMI
  • Publication number: 20180372184
    Abstract: In a friction transmission belt including a rubber layer forming a pulley contact surface, the rubber layer includes a rubber composition containing polyolefin particles and an inorganic filler. In the rubber composition, a total content of the polyolefin particles and the inorganic filler with respect to 100 parts by mass of a rubber component is 85 parts by mass or more.
    Type: Application
    Filed: August 30, 2018
    Publication date: December 27, 2018
    Applicant: BANDO CHEMICAL INDUSTRIES, LTD.
    Inventors: Takayuki OKUBO, Shinji TAKAHASHI, Hideaki KAWAHARA
  • Publication number: 20180372183
    Abstract: In a friction transmission belt including a rubber layer forming a pulley contact surface, the rubber layer includes a rubber composition containing hydrophilic inorganic filler and a sliding-resistant material. The sliding-resistant material protrudes from the pulley contact surface, and is at least one of hydrophobic resin particles and hydrophobic resin fibers having an official regain of 0.4% or below, and in the rubber composition, a content of the hydrophilic inorganic filler with respect to 100 parts by mass of the rubber component is 35 parts by mass or more.
    Type: Application
    Filed: August 30, 2018
    Publication date: December 27, 2018
    Applicant: BANDO CHEMICAL INDUSTRIES, LTD.
    Inventors: Takayuki OKUBO, Shinji TAKAHASHI, Hideaki KAWAHARA
  • Publication number: 20180358258
    Abstract: A method of forming an integrated circuit includes forming ?1 hard mask layer on a device layer on a BOX layer of a SOI substrate. A patterned masking layer is used for a trench etch to simultaneously form larger and smaller area trenches through the hard mask layer, device layer and the BOX layer. A dielectric liner is formed for lining the larger and smaller area trenches. A dielectric layer is deposited for completely filling the smaller area trenches and only partially filling the larger area trenches. The larger area trenches are bottom etched through the dielectric layer to provide a top side contact to the handle portion. The handle portion at a bottom of the larger area trenches is implanted to form a handle contact, and the larger area trenches are completely filled with an electrically conductive layer to form a top side ohmic contact to the handle contact.
    Type: Application
    Filed: June 9, 2017
    Publication date: December 13, 2018
    Inventors: ZACHARY K. LEE, ROBERT GRAHAM SHAW, HIDEAKI KAWAHARA, ASAD MAHMOOD HAIDER, YUJI MIZUGUCHI, HIROSHI YAMASAKI, ABBAS ALI, BRIAN GOODLIN
  • Patent number: 10134830
    Abstract: A deep trench capacitor and a method for providing the same in a semiconductor process are disclosed. The method includes forming a plurality of deep trenches in a first region of a semiconductor wafer, the first region having well doping of a first type. A dielectric layer is formed on a surface of the plurality of deep trenches and a doped polysilicon layer is deposited to fill the plurality of deep trenches, with the doped polysilicon being doped with a dopant of a second type. Shallow trench isolation is formed overlying the dielectric layer at an intersection of the dielectric layer with the surface of the semiconductor wafer.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: November 20, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Binghua Hu, Hideaki Kawahara, Sameer P. Pendharkar
  • Publication number: 20180327629
    Abstract: Provided are a curing agent for epoxy resins, which is a curing agent capable of curing an epoxy resin at room temperature, and which can form a cured product (cured coating film) having excellent adhesion even to a substrate which is not in an environment completely dried, and an epoxy resin composition obtained using the same. A curing agent for epoxy resins, containing (a1) an aromatic amine, (a2) an aliphatic amine having an aromatic ring or a cycloalkane ring, and (a3) a curing accelerator, and an epoxy resin composition containing the curing agent and an epoxy resin.
    Type: Application
    Filed: November 12, 2015
    Publication date: November 15, 2018
    Applicant: DIC Corporation
    Inventors: Tsugio Tomura, Hiroshi Moriyama, Hideaki Kawahara
  • Publication number: 20180326680
    Abstract: A friction transmission belt has a rubber layer forming a pulley contacting portion. The rubber layer is made of a rubber composition containing a crosslinked rubber component and crosslinked polyolefin particles. Examples of the crosslinked polyolefin particles can contain ultrahigh molecular weight polyolefin particles having an average molecular weight of 500,000 or more.
    Type: Application
    Filed: July 20, 2018
    Publication date: November 15, 2018
    Inventors: Takayuki Okubo, Hisashi Matsuda, Hideaki Kawahara, Shinji Takahashi
  • Publication number: 20180226502
    Abstract: A device includes a transistor formed on a substrate. The transistor includes an n-type drain contact layer, an n-type drain layer, an oxide layer, a p-type body region, a p-type terminal region, body trenches, and terminal trenches. The n-type drain contact layer is near a bottom surface of the substrate. The n-type drain layer is positioned on the n-type drain contact layer. The oxide layer circumscribes a transistor region. The p-type body region is positioned within the transistor region. The p-type terminal region extends from under the oxide layer to an edge of the transistor region, thereby forming a contiguous junction with the p-type body region. The body trenches is within the transistor region and interleaves with the p-type body region, whereas the terminal trenches is outside the transistor region and interleaves with the p-type terminal region.
    Type: Application
    Filed: February 8, 2017
    Publication date: August 9, 2018
    Inventors: Hideaki Kawahara, Christopher Boguslaw Kocon, Seetharaman Sridhar, Simon John Molloy, Satoshi Suzuki
  • Patent number: 9927002
    Abstract: A friction transmission belt includes a belt body, formed of a rubber composition, looped over a pulley, and transmitting power. The friction transmission belt includes a reinforcing fabric wrapping at least a surface, of the belt body, in contact with the pulley. The reinforcing fabric is a knitted fabric, and on the surface of the belt body in contact with the pulley, a wale direction of the reinforcing fabric is a direction in which the friction transmission belt travels.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: March 27, 2018
    Assignee: BANDO CHEMICAL INDUSTRIES, LTD.
    Inventors: Sungjin Kim, Hideaki Kawahara, Osamu Takahashi
  • Publication number: 20180076277
    Abstract: A deep trench capacitor and a method for providing the same in a semiconductor process are disclosed. The method includes forming a plurality of deep trenches in a first region of a semiconductor wafer, the first region having well doping of a first type. A dielectric layer is formed on a surface of the plurality of deep trenches and a doped polysilicon layer is deposited to fill the plurality of deep trenches, with the doped polysilicon being doped with a dopant of a second type. Shallow trench isolation is formed overlying the dielectric layer at an intersection of the dielectric layer with the surface of the semiconductor wafer.
    Type: Application
    Filed: September 13, 2016
    Publication date: March 15, 2018
    Inventors: Binghua Hu, Hideaki Kawahara, Sameer P. Pendharkar
  • Publication number: 20180061932
    Abstract: An integrated trench capacitor and method for making the trench capacitor is disclosed. The method includes forming a trench in a silicon layer, forming a first dielectric on the exposed surface of the trench, performing an anisotropic etch of the first dielectric to expose silicon at the bottom of the trench, implanting a dopant into exposed silicon at the bottom of the trench, forming a first polysilicon layer over the first dielectric, forming a second dielectric over the first polysilicon layer, and forming a second polysilicon layer over the second dielectric to fill the trench.
    Type: Application
    Filed: August 24, 2016
    Publication date: March 1, 2018
    Inventors: Hideaki Kawahara, Binghua Hu, Sameer Pendharkar
  • Patent number: 9905638
    Abstract: A method of forming a semiconductor device includes etching a high aspect ratio, substantially perpendicular trench in a semiconductor region doped with a first dopant having first conductivity type and performing a first cycle for depositing silicon doped with a second dopant on an inner surface of the high aspect ratio, substantially perpendicular trench, the first cycle comprising alternately depositing silicon at a first constant pressure and etching the deposited silicon at an etching pressure that ramps up from a first value to a second value, the second dopant having a second conductivity type that is opposite from the first conductivity type.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: February 27, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Tatsuya Tominari, Satoshi Suzuki, Seetharaman Sridhar, Christopher Boguslaw Kocon, Simon John Molloy, Hideaki Kawahara
  • Publication number: 20170288052
    Abstract: A semiconductor device contains a vertical MOS transistor having a trench gate in trenches extending through a vertical drift region to a drain region. The trenches have field plates under the gate; the field plates are adjacent to the drift region and have a plurality of segments. A dielectric liner in the trenches separating the field plates from the drift region has a thickness great than a gate dielectric layer between the gate and the body. The dielectric liner is thicker on a lower segment of the field plate, at a bottom of the trenches, than an upper segment, immediately under the gate. The trench gate may be electrically isolated from the field plates, or may be connected to the upper segment. The segments of the field plates may be electrically isolated from each other or may be connected to each other in the trenches.
    Type: Application
    Filed: June 14, 2017
    Publication date: October 5, 2017
    Inventors: Hideaki Kawahara, Seetharaman Sridhar, Christopher Boguslaw Kocon, Simon John Molloy, Hong Yang