Abstract: The present invention provides a luminescence measuring method that can be accurately and quickly carried out while inhibiting a possible background associated with viable bacteria adhering to a nozzle or Adenosine Tri Phosphate remaining in the nozzle, and an apparatus for the method. The present invention uses a washing apparatus characterized by including a nozzle, a lysys solution, a luminescence reagent solution, and a detection section, as well as a relevant washing method and a relevant luminescence measuring method. To remove viable bacteria adhering to the nozzle, the nozzle is immersed in the lysys solution and then in the luminescence reagent solution. The detection section monitors luminescence occurring during a washing process.

Abstract: Beads having diameters of several tens of micrometers to several millimeters and immobilized with biomolecules are captured by one kind of bead capturing nozzle one by one without fail. Using a bead holding plate having a plurality of wells each of which holds a plurality of the beads and a solution, a vibration generator mounted with a stage to attach the bead holding plate, and a bead capturing nozzle for bead capture connected to a suction pump, only a single bead is captured at the tip of the bead capturing nozzle by inserting the nozzle having an inner diameter smaller than the beads and a negative pressure inside created by the pump into the solution to allow the nozzle to come in contact with the beads in the well, applying a vibration to the bead holding plate by the vibration generator, and withdrawing the bead capturing nozzle into the air.

Abstract: A CAM unit has a memory array for storing storage data, and a RAM unit has a memory array for storing the same storage data and check bits added thereto for determining whether the storage data in its memory array has an error. An error correction circuit uses the check bits to correct any error of data read from the memory array of the RAM unit and rewrite the error-corrected data to the memory arrays. Even if a soft error occurs in the storage data, the check bits can be used to correct the error in the data and rewrite the error-corrected data. Thus, a matching comparison can be performed on the storage data with high reliability.

Abstract: A CAM unit has a memory array for storing storage data, and a RAM unit has a memory array for storing the same storage data and check bits added thereto for determining whether the storage data in its memory array has an error. An error correction circuit uses the check bits to correct any error of data read from the memory array of the RAM unit and rewrite the error-corrected data to the memory arrays. Even if a soft error occurs in the storage data, the check bits can be used to correct the error in the data and rewrite the error-corrected data. Thus, a matching comparison can be performed on the storage data with high reliability.

Abstract: The invention provides a method in which an annular or spiral droplet holder formed of wire is used to hold a droplet in a state of being hung therefrom or being contained therein. A means for moving the droplet holder is added to the droplet holder to enable droplet transfer. To merge two droplets, they are brought into contact. To drip the droplet held by a droplet holder formed of wire, the droplet holder is deformed using an external force. A light path which passes through a droplet is set to enable optical measurement. The present invention enables inexpensive, simple droplet transfer. An inexpensive, simple configuration for handling droplets in the fields of chemical analysis, biochemical analysis, and automatic blood analysis can be realized according to the present invention.

Abstract: In a parallel operational processing device having an operational processing unit arranged between memory blocks each having a plurality of memory cells arranged in rows and columns, the respective columns of each memory block are alternately connected to the operational processing units on the opposite sides of the memory block. By selecting one word line in one memory block, data can be transferred to two operational processing units. The number of the word lines selected per one operational processing unit is reduced, and power consumption is reduced. The bit operation units and sense amplifiers/write drivers of the operational processing units have arrangement pitch conditions mitigated and are reduced in number, and an isolation region between the memory blocks is not required and the layout area is reduced. Thus, the parallel operational processing device with a layout area and the power consumption reduced, can achieve a fast operation.

Abstract: A CAM (Content Addressable Memory) cell includes first and second data storage portions storing data, horizontal port write gates for storing data applied through a match line pair in the data storage portions in a data write through a horizontal port, and search/read gates for driving the match lines of the match line pair in accordance with the data stored in the data storage portions in a search operation and in a data read through the horizontal port. The match lines are used as horizontal bit line pair, or signal lines for accessing the horizontal port. As the first and second data storage portions are used, it becomes possible to store ternary data, and accordingly, a write mask function of inhibiting a data write at a destination of data transfer is realized. Further, as the CAM cell is used, an arithmetic/logic operation following a search process can be executed selectively, and high speed data writing/reading becomes possible.

Abstract: There are provided a novel method and technology for arraying micro-particles. Micro-particle trapping capillaries each having an inner diameter smaller than the outer diameter of probe-immobilized micro-particles are prepared. By vacuuming the inside of each micro-particle trapping capillary, only one of the micro-particles is vacuumed onto an opening at the tip thereof and taken out from holders holding a plurality of the micro-particles. The micro-particle vacuumed onto the opening at the tip of each micro-particle trapping capillary is positioned at the opening of the capillary or the edge of each channel provided in a chip, the channels each having an inlet and an outlet with a slightly larger width than the outer diameter of the micro-particle so as to allow passage of only one micro-particle. The micro-particle vacuumed onto the opening at the capillary tip is injected into the capillary from the opening of the capillary or the channel edge of the chip.

Abstract: A memory cell of a nonvolatile semiconductor memory device is formed on a silicon layer formed on a silicon substrate through an ONO film. The memory cell has a source region and a drain region formed in the silicon layer, an ONO film and a gate electrode. The ONO film and the ONO film include nitride films having charge trap parts trapping charges.

Abstract: Beads having diameters of several tens of micrometers to several millimeters and immobilized with biomolecules are captured by one kind of bead capturing nozzle one by one without fail. Using a bead holding plate having a plurality of wells each of which holds a plurality of the beads and a solution, a vibration generator mounted with a stage to attach the bead holding plate, and a bead capturing nozzle for bead capture connected to a suction pump, only a single bead is captured at the tip of the bead capturing nozzle by inserting the nozzle having an inner diameter smaller than the beads and a negative pressure inside created by the pump into the solution to allow the nozzle to come in contact with the beads in the well, applying a vibration to the bead holding plate by the vibration generator, and withdrawing the bead capturing nozzle into the air.

Abstract: In a memory circuit, a transistor formed in the same process as that of a logic transistor is used for peripheral circuitry except for a region to be supplied with high voltage. Thus, the manufacturing process can be simplified and a logic-merged memory operating at a high speed is provided.

Abstract: An orthogonal memory for transforming arrangements of system bus data and processing data is placed between a system bus interface and a memory cell mat storing the processing data. The orthogonal memory includes two-port memory cells, and changes data train transferred in a bit parallel and word serial fashion into a data train of word parallel and bit serial data. Data transfer efficiency in a signal processing device performing parallel operational processing can be increased without impairing parallelism of the processing.

Abstract: There will be provided a chemical reaction device and a chemical reaction apparatus capable of performing transverse liquid movement in a simple structure and at low cost without causing contamination and air bubbles. There will be installed a mechanism for supporting the chemical reaction device in any other position than a center of a turntable which can be rotated, for moving liquid by a centrifugal force due to rotation, and for reversing a direction of the flow path independently of the turntable.

Abstract: The present invention provides a content addressable memory (CAM) with no problem in operation speed reduction and with small power consumption on an SOI substrate. The CAM includes a data memory part DM and a data comparison part DC which compares data provided on a search line SL with data stored in the data memory part DM. In the case of a mismatch, a match line ML precharged to H level is discharged to be L level. Here, gates and bodies of respective NMOS transistors N6 and N8, which constitute data comparison part DC, are short-circuited to lower threshold voltages of NMOS transistors N6 and N8. Therefore, even if lowering of voltage of search line SL connected to gate is performed, turn-on current of MOS transistors N6 and N8 can be increased to discharge the match line ML with high speed. As a result, even if lowering of power consumption of the search line SL is performed to lower power consumption, a CAM with no problem in operation speed reduction can be realized.

Abstract: A CAM unit has a memory array for storing storage data, and a RAM unit has a memory array for storing the same storage data and check bits added thereto for determining whether the storage data in its memory array has an error. An error correction circuit uses the check bits to correct any error of data read from the memory array of the RAM unit and rewrite the error-corrected data to the memory arrays. Even if a soft error occurs in the storage data, the check bits can be used to correct the error in the data and rewrite the error-corrected data. Thus, a matching comparison can be performed on the storage data with high reliability.

Abstract: A memory cell mat is divided into a plurality of entries, and an arithmetic logic unit is arranged corresponding to each entry. Between the entries and the corresponding arithmetic logic units, arithmetic/logic operation is executed in bit-serial and entry-parallel manner. Where parallel operation is not very effective, data is transferred in entry-serial and bit-parallel manner to a group of processors provided at a lower portion of the memory mat. In this manner, a large amount of data can be processed at high speed regardless of the contents of operation or data bit width.

Abstract: This invention provides a method of genetic testing that enables testing of a plurality of variation sites (SNPs) in a cost-effective and simple manner, allowing realization of genetic diagnosis in clinical settings. The SNP type of the nucleic acid sample is evaluated by: allowing a nucleic acid sample having an anchor sequence at its 5? end to hybridize to a support having, immobilized on its surface, a probe containing a sequence that is complementary to the target sequence (the SNP region); extending a complementary strand from the probe utilizing the nucleic acid sample as a template; dissociating and removing the nucleic acid sample from the extended probe; extending a complementary strand using the extended probe as a template and a primer having a sequence identical to the anchor sequence; and detecting pyrophosphoric acid generated via the primer extension, based on bioluminescence.

Abstract: An XOR gate receives an input from a pair of read data lines to output a self-precharge signal when there is an increased potential difference between the paired read data lines. Thus, immediately after the increased potential difference between the paired read data lines occurs upon issuance of a read command, a precharge operation is autonomically performed. Therefore, no external precharge command is necessary when the read command is issued and thus a higher-speed operation is easily achieved.

Abstract: A shift information latch circuit includes a plurality of latch portions provided corresponding to memory cell rows, respectively, and a fuse circuit transmitting fuse data produced corresponding to an address of a faulty memory cell row. The plurality of latch portion successively receive fuse data, and each transmit a shift control signal instructing a shift operation. In response to this shift control signal, a row decoder and a match line amplifier execute a shift operation for repairing the faulty memory cell row. In this structure, a decoder circuit decoding the address of the faulty memory cell row is not arranged so that a whole area of the circuits executing the shift operation is reduced, and the shift operation can be easily executed.

Abstract: A chemical reaction device is provided for a chemical reaction between molecules immobilized on a solid phase and molecules in a solution, and a chemical analysis device is also provided to capture molecules in the solution by molecules immobilized on the solid phase through a chemical reaction and subsequent measurement of the captured molecules. Reaction efficiency as well as sample throughput are thereby improved. The chemical reaction device and the chemical analysis device use a channel of a microfluidic device for a reaction vessel, and at least a particular molecule is immobilized on an interior surface and a fixed structure or a non-fixed obstacle against a flow is provided in the channel.