Abstract: An anode material capable of providing a high capacity and improving cycle characteristics and a manufacturing method thereof, and a battery are provided. The anode material has a reaction phase containing an element capable of generating an intermetallic compound with Li and C. In this reaction phase, a half value width of a diffraction peak by X-ray diffraction is preferably 0.5° or more. Further, in this anode material, it is preferable that a peak of C is obtained in a region lower than 284.5 eV by XPS. In the case that Sn is contained as an element capable of generating an intermetallic compound with Li, it is preferable that an energy difference between a peak of 3d5/2 orbit of Sn and a peak of 1s orbit of C is larger than 200.1 eV. It becomes thereby possible that cohesion or crystallization of the element capable of generating an intermetallic compound with Li associated with charge and discharge can be inhibited.

Abstract: A write-driver/read-amplifier circuit includes a write driver, a GIO equalize circuit and a read amplifier. When a current leaks from or to global data line, a signal applied to a logic gate attains L-level. As a result, the write driver and the GIO equalize circuit stop the operations so that a semiconductor memory device can prevent occurrence of an unnecessary leak current.

Abstract: Disclosed is a non-aqueous electrolyte secondary battery having an excellent preservation characteristic at a high temperature and charging/discharging cycle characteristic. A rolled body in which a strip-shape positive electrode and negative electrode are rolled with a separator in-between is provided inside a battery can. The positive electrode contains LixMn2-yMayO4 (where, Ma is at least one element selected from the group consisting of metal elements other than Mn, and B) and LiNi1-zMbzO2 (where, Mb is at least one element selected from the group consisting of metal elements other than Ni, and B). By replacing part of Mn and Ni with other elements, the crystal structure can be stabilized. Thereby, the capacity retention ratio after preservation at a high temperature, and a heavy load discharging power under a high electric potential cutoff can be improved.

Abstract: An internal power supply potential generation circuit includes an overcharge prevention circuit connected to an internal power supply node. The overcharge prevention circuit includes a circuit outputting a signal to be determined that is determined by an internal power supply potential, a differential amplification circuit amplifying a difference in potential between the signal to be determined and a reference potential for output to a node as a signal indicating that current should be drawn, and a current draw circuit drawing current from the internal power supply node in response to the signal indicating that current should be drawn. Thus the semiconductor integrated circuit device of interest can provide a steady internal power supply potential.

Abstract: Disclosed is a non-aqueous electrolyte secondary battery having an excellent preservation characteristic at a high temperature and charging/discharging cycle characteristic. A rolled body in which a strip-shape positive electrode and negative electrode are rolled with a separator in-between is provided inside a battery can. The positive electrode contains LixMn2-yMayO4 (where, Ma is at least one element selected from the group consisting of metal elements other than Mn, and B) and LiNi1-zMbzO2 (where, Mb is at least one element selected from the group consisting of metal elements other than Ni, and B). By replacing part of Mn and Ni with other elements, the crystal structure can be stabilized. Thereby, the capacity retention ratio after preservation at a high temperature, and a heavy load discharging power under a high electric potential cutoff can be improved.

Abstract: A dummy cell has a plurality of dummy magneto-resistance elements which have the same characteristic as a magneto-resistance element, which characteristic changes corresponding to a voltage applied to the opposite ends. In addition, a voltage applied to opposite ends of each dummy magneto-resistance element is made smaller than a voltage applied to opposite ends of a magneto-resistance element of a memory cell. With this, the dummy cell is designed so as to have an intermediate electric resistance between first and second electric resistances.

Abstract: During data reading, a sense enable signal is activated to start charging of a data line prior to formation of a current path including the data line and a selected memory cell in accordance with row and column selecting operations. Charging of the data line is completed early so that it is possible to reduce a time required from start of the data reading to such a state that a passing current difference between the data lines reaches a level corresponding to storage data of the selected memory cell, and the data reading can be performed fast.

Abstract: In one data read operation, data read for reading stored data before and after a predetermined data write magnetic field is applied to a selected memory cell, respectively, is executed, and the data read is executed in accordance with comparison of voltage levels corresponding to the data read operations before and after application of the predetermined data write magnetic field. In addition, data read operations before and after the application of a data write magnetic field are executed using read modify write. It is thereby possible to avoid an influence of an offset or the like resulting from manufacturing irregularities in respective circuits forming a data read path, to improve efficiency of the data read operation with accuracy and to execute a high rate data read operation.

Abstract: An alloy powder containing at least one element selected from the group consisting of the Group 14 elements exclusive of C and the Group 13 elements exclusive of Tl is subjected to a mechanical milling treatment, to obtain a negative electrode active material. Alternately, a raw material including a powder containing at least one element selected from the group consisting of the Group 14 elements exclusive of C and the Group 13 elements exclusive of Tl is subjected to a mechanical alloying treatment at a reaction temperature of below 90° C., to obtain a negative electrode active material.

Abstract: A plurality of bit lines are divided into a plurality of groups each including Y (Y: integer of at least two) bit lines. Y data read data lines passing a data read current therethrough in data reading are provided along with Y connection control parts electrically coupling Y bit lines and the Y read data lines with each other every group. Therefore, the connection control parts electrically connected with the Y read data lines are uniformly divided so that parasitic capacitance applied to the read data lines following electrical connection with the connection control parts can be suppressed. Therefore, the time for charging the read data lines to a prescribed voltage level can be reduced for executing high-speed data reading.

Abstract: During data reading, a sense enable signal is activated to start charging of a data line prior to formation of a current path including the data line and a selected memory cell in accordance with row and column selecting operations. Charging of the data line is completed early so that it is possible to reduce a time required from start of the data reading to such a state that a passing current difference between the data lines reaches a level corresponding to storage data of the selected memory cell, and the data reading can be performed fast.

Abstract: In a memory cell array of an MRAM, a reference memory cell holding a reference value can generate accurate reference current of an intermediate value of data by uniformly supplying reference current to two sense amplifiers using two cells of a cell holding “H” data and a cell holding “L” data. Each bit line is connected to a data-storing memory cell and to the reference memory cell. When the data-storing memory cell connected to a bit line is accessed, the reference memory cell is accessed on the adjacent bit line. Only one row of reference memory cells is provided, reducing the chip area. Therefore, a non-volatile memory device that can reduce the area of a reference cell occupied on a chip while generating accurate reference current for determination can be provided.

Abstract: Peripheral circuitry writes/reads input data and output data of L bits (L: integer of at least 2) that is input/output to/from a data node into/from first and second memory cell blocks that are selectively accessed. The peripheral circuitry uses circuit components operating in response to a clock signal to write/read the data by dividing the data writing operation/data reading operation into a plurality of stages and carrying out them in pipelining manner.

Abstract: In a sense amplifier, local I/O lines are maintained at a predetermined voltage by transistors. Transistors forming a current mirror supply an operating current according to a passing current which flows through transistors, to sense nodes. Transistors forming a current mirror extract an operating current according to the passing current which flows through transistors, from sense nodes. As a result, a voltage difference is generated in sense nodes in accordance with the operating current difference.

Abstract: Provided are an anode material capable of improving a capacity and cycle characteristics, and a battery using the anode material. A disk-shaped cathode contained in a package can and a disk-shaped anode contained in a package cup are laminated with a separator in between. The anode comprises a composite material formed through applying a compressive force and a shearing force to at least a part of a surface of a base material including at least one kind selected from Group 14 elements except for carbon so as to combine a carbonaceous material with the base material, thereby the capacity and the cycle characteristics can be improved.

Abstract: In a sense amplifier, local I/O lines are maintained at a predetermined voltage by transistors. Transistors forming a current mirror supply an operating current according to a passing current which flows through transistors, to sense nodes. Transistors forming a current mirror extract an operating current according to the passing current which flows through transistors, from sense nodes. As a result, a voltage difference is generated in sense nodes in accordance with the operating current difference.

Abstract: In a data read operation, a selected memory cell and a reference memory cell are connected to complementary first and second data lines via complementary first and second bit lines, respectively. A differential amplifier supplies passing currents of the memory cell and the reference cell to complementary first and second data buses, and amplifies a passing current difference between the first and second data buses occurring corresponding to an electric resistance difference between the memory cell and reference cell to produce a voltage difference of a polarity corresponding to the level of the stored data of the selected memory cell between first and second nodes.

Abstract: An alloy powder containing at least one element selected from the group consisting of the Group 14 elements exclusive of C and the Group 13 elements exclusive of Tl is subjected to a mechanical milling treatment, to obtain a negative electrode active material. Alternately, a raw material including a powder containing at least one element selected from the group consisting of the Group 14 elements exclusive of C and the Group 13 elements exclusive of Tl is subjected to a mechanical alloying treatment at a reaction temperature of below 90° C., to obtain a negative electrode active material.

Abstract: In DRAM, a bit line pair are connected to the respective gates of an N channel MOS transistor pair of a read gate, and a write data line pair are connected to the respective gates of an N channel MOS transistor pair of a write gate. Therefore, since neither of the read data line pair and the write data line pair is directly connected to the bit line pair, no data signal on the bit line pair is destroyed by noise occurring on the read data line pair and the write data line pair.

Abstract: A plurality of bit lines are divided into a plurality of groups each including Y (Y: integer of at least two) bit lines. Y data read data lines passing a data read current therethrough in data reading are provided along with Y connection control parts electrically coupling Y bit lines and the Y read data lines with each other every group. Therefore, the connection control parts electrically connected with the Y read data lines are uniformly divided so that parasitic capacitance applied to the read data lines following electrical connection with the connection control parts can be suppressed. Therefore, the time for charging the read data lines to a prescribed voltage level can be reduced for executing high-speed data reading.