Abstract: Provided is a battery with a higher capacity and superior charge-discharge cycle characteristics. A cathode contained in a package can and an anode contained in a package cup are laminated with a separator in between. The separator is impregnated with an electrolyte solution formed by dissolving lithium salt in a solvent. The anode comprises a tin-containing material including metallic tin and an intermetallic compound including tin in the same particle. A higher capacity and superior charge-discharge cycles can be obtained by the tin-containing material.

Abstract: A memory system that generates a reference voltage unaffected by supply voltage variations and is suitable for performing burn-in test is attainable by employing the following configuration. For example, in an MRAM containing a TMR element (Rij) and an N channel MOS transistor (Mij), as memory element, there is disposed a switching circuit (SW1) capable of switching between the state of applying a reference voltage (VrefN) to a memory element and the state of applying a reference voltage (VrefB) for burn-in test having a larger value than the reference voltage (VrefN) to the memory element. At the time of burn-in test, instead of the reference voltage (VrefN) for normal read operation, the reference voltage (VrefB) for burn-in test can be applied via a sense circuit (SC) to the memory element, by applying mode change signals (MODE1 to MODEn) from the exterior and operating the switching circuit (SW1) via a decode circuit (TD).

Abstract: In one data read operation, data read for reading stored data before and after a predetermined data write magnetic field is applied to a selected memory cell, respectively, is executed, and the data read is executed in accordance with comparison of voltage levels corresponding to the data read operations before and after application of the predetermined data write magnetic field. In addition, data read operations before and after the application of a data write magnetic field are executed using read modify write. It is thereby possible to avoid an influence of an offset or the like resulting from manufacturing irregularities in respective circuits forming a data read path, to improve efficiency of the data read operation with accuracy and to execute a high rate data read operation.

Abstract: In a memory cell array of an MRAM, a reference memory cell holding a reference value can generate accurate reference current of an intermediate value of data by uniformly supplying reference current to two sense amplifiers using two cells of a cell holding “H” data and a cell holding “L” data. Each bit line is connected to a data-storing memory cell and to the reference memory cell. When the data-storing memory cell connected to a bit line is accessed, the reference memory cell is accessed on the adjacent bit line. Only one row of reference memory cells is provided, reducing the chip area. Therefore, a non-volatile memory device that can reduce the area of a reference cell occupied on a chip while generating accurate reference current for determination can be provided.

Abstract: Peripheral circuitry writes/reads input data and output data of L bits (L: integer of at least 2) that is input/output to/from a data node into/from first and second memory cell blocks that are selectively accessed. The peripheral circuitry uses circuit components operating in response to a clock signal to write/read the data by dividing the data writing operation/data reading operation into a plurality of stages and carrying out them in pipelining manner.

Abstract: A non-aqueous electrolyte battery includes an cathode having an cathode mixture layer containing an cathode active material; an anode having an anode mixture layer containing an anode active material which includes a first active material and/or a second active material, where the first active material includes a metal, alloy or compound capable of react with lithium, and the second active material includes a carbonaceous material; and a non-aqueous electrolytic solution. By allowing the anode to contain the first active material in a predetermined amount, and by controlling the packing ratio of the anode mixture layer, the anode is successfully prevented from being degraded due to expansion-and-shrinkage of the anode active material in response to the charge/discharge cycle, and thus degradation of the charge/discharge characteristics of the battery is suppressed.

Abstract: A non-aqueous electrolyte secondary battery having a large discharge capacity and improved charge/discharge cycle characteristics is disclosed. The battery has a negative electrode which comprises a negative electrode active material composed of an element or a compound of the element capable of reacting with lithium, and a negative electrode current collector, where the negative electrode active material contains at least carbon black.

Abstract: A memory system that generates a reference voltage unaffected by supply voltage variations and is suitable for performing burn-in test is attainable by employing the following configuration. For example, in an MRAM containing a TMR element (Rij) and an N channel MOS transistor (Mij), as memory element, there is disposed a switching circuit (SW1) capable of switching between the state of applying a reference voltage (VrefN) to a memory element and the state of applying a reference voltage (VrefB) for burn-in test having a larger value than the reference voltage (VrefN) to the memory element. At the time of burn-in test, instead of the reference voltage (VrefN) for normal read operation, the reference voltage (VrefB) for burn-in test can be applied via a sense circuit (SC) to the memory element, by applying mode change signals (MODE1 to MODEn) from the exterior and operating the switching circuit (SW1) via a decode circuit (TD).

Abstract: A method of manufacturing a negative material and a secondary battery in which a belt-shaped positive electrode and a belt-shaped negative electrode are wound together with a separator in between them to form a wound electrode body. The wound electrode battery is then inserted inside a battery can. Preferably, the negative electrode is produced with crushed silicon or a silicon compound in an oxygen partial pressure atmosphere within a value from higher than 10 Pa to lower than an oxygen partial pressure of air.

Abstract: The present invention provides a non-aqueous electrolyte secondary cell including: a lithium-nickel composite oxide as a cathode active material and a material having a specific surface in the range from 0.05 m2/g to 2 m2/g as an anode active material. When A is assumed to be the weight of the lithium-nickel composite oxide and B is assumed to be the weight of the cathode active material other than the lithium-nickel composite oxide, the mixture ratio R expressed A/(A+B) is in the range from 0.2 to 1. This combination of the cathode active material and the anode active material enables to obtain an improved anti-over discharge characteristic even when an anode current collector contains Cu.

Abstract: A dummy cell has a plurality of dummy magneto-resistance elements which have the same characteristic as a magneto-resistance element, which characteristic changes corresponding to a voltage applied to the opposite ends. In addition, a voltage applied to opposite ends of each dummy magneto-resistance element is made smaller than a voltage applied to opposite ends of a magneto-resistance element of a memory cell. With this, the dummy cell is designed so as to have an intermediate electric resistance between first and second electric resistances.

Abstract: During data reading, a sense enable signal is activated to start charging of a data line prior to formation of a current path including the data line and a selected memory cell in accordance with row and column selecting operations. Charging of the data line is completed early so that it is possible to reduce a time required from start of the data reading to such a state that a passing current difference between the data lines reaches a level corresponding to storage data of the selected memory cell, and the data reading can be performed fast.

Abstract: Normal memory cells and dummy cells are arranged continuously in a memory array. In a data read operation, first and second data lines are connected to the selected memory cell and the dummy cell, respectively, and are supplied with operation currents of a differential amplifier. An offset corresponding to a voltage difference between first and second offset control voltages applied from voltage generating circuits are provided between passing currents of the first and second data lines, and a reference current passing through the dummy cell is set to a level intermediate between two kinds of levels corresponding to storage data of a data read current passing through the selected memory cell.

Abstract: The present invention relates to a nonaqueous electrolyte secondary battery comprising an anode (3), a cathode (2) and a nonaqueous electrolyte. The anode forming this battery includes composite particles having a carbon material included in a metallic material. As the metallic material, metal capable of electrochemically reacting with lithium in a nonaqueous electrolyte is included.

Abstract: A driving circuit includes a voltage converting circuit receiving a block selection signal and converting to a signal of a boosted potential level, and first and second N channel MOS transistors connected in series between the boosted potential and the ground potential. The gate of the first transistor receives the boosted potential, and a potential level at a connection node between the first and second transistors is provided as a signal BLI (i, 0).

Abstract: In a data read operation, a selected memory cell and a reference memory cell are connected to complementary first and second data lines via complementary first and second bit lines, respectively. A differential amplifier supplies passing currents of the memory cell and the reference cell to complementary first and second data buses, and amplifies a passing current difference between the first and second data buses occurring corresponding to an electric resistance difference between the memory cell and reference cell to produce a voltage difference of a polarity corresponding to the level of the stored data of the selected memory cell between first and second nodes.

Abstract: A read gate of a DRAM core cell includes first and second N channel MOS transistors having gates connected to a pair of bit lines through first and second nodes, respectively, and third and fourth MOS transistors having gates both of which receive a column selecting signal, with gate oxide films of the third and the fourth N channel MOS transistors being formed to be thinner than gate oxide films of the first and the second N channel MOS transistors. It is accordingly possible to lower an amplitude voltage of the column selecting signal, thereby enabling reduction of electric current consumption and speed-up of an operating rate of the DRAM core cell.

Abstract: A read data line pair is arranged for every four memory cell columns. Column selection in data reading is carried out by four sub read source lines. A write data line pair is arranged for every eight memory cell columns. Column selection in a data write operation is carried out by eight sub write activation lines. By differentiating the number between the read data line pairs and the write data line pairs and the corresponding memory cell columns, the wiring pitch of the data lines can be alleviated to suppress parasitic capacitance while avoiding significant increase of the signal lines to execute column selection.

Abstract: In DRAM, a bit line pair are connected to the respective gates of an N channel MOS transistor pair of a read gate, and a write data line pair are connected to the respective gates of an N channel MOS transistor pair of a write gate. Therefore, since neither of the read data line pair and the write data line pair is directly connected to the bit line pair, no data signal on the bit line pair is destroyed by noise occurring on the data line pair.

Abstract: A write-driver/read-amplifier circuit includes a write driver, a GIO equalize circuit and a read amplifier. When a current leaks from or to global data line, a signal applied to a logic gate attains L-level. As a result, the write driver and the GIO equalize circuit stop the operations so that a semiconductor memory device can prevent occurrence of an unnecessary leak current.