Patents by Inventor Hiroshi Tanabe

Hiroshi Tanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140166206
    Abstract: A non-plasma dry etching apparatus is capable of forming textures uniformly only on one side of a silicon substrate. The non-plasma dry etching apparatus includes a stage on which a silicon substrate is placed is used as a base including plural layers. The plural layers include an electrostatic chuck layer, a heat-resistant glass layer and a space layer from the side on which the silicon substrate is placed.
    Type: Application
    Filed: November 7, 2013
    Publication date: June 19, 2014
    Applicant: Panasonic Corporation
    Inventors: NAOSHI YAMAGUCHI, HIROSHI TANABE, ICHIRO NAKAYAMA
  • Patent number: 8743317
    Abstract: An image forming apparatus includes: a functional element substrate to which a pixel is formed in a predetermined cycle; an opposed substrate formed on the functional element substrate; and an optical device arranged on the opposed substrate, which includes a transparent layer and an optical absorption layer arranged in a cycle of 1/n (n is an integer number) of the cycle of arranging the pixel, and restricts spread of transmitted light.
    Type: Grant
    Filed: October 13, 2010
    Date of Patent: June 3, 2014
    Assignee: NLT Technologies, Ltd.
    Inventors: Kunihiro Shiota, Koji Mimura, Hiroshi Tanabe, Koji Shigemura
  • Patent number: 8723240
    Abstract: A manufacturing method for a semiconductor device, the method including forming a thin film transistor by forming a polysilicon thin film on an insulating substrate, forming a gate electrode via a gate insulating film, and forming source/drain regions and a channel region by ion implantation in the polysilicon thin film by using the gate electrode as a mask, forming an interconnection layer on an interlayer dielectric film covering this thin film transistor and forming a first contact to be connected to the thin film transistor through the interlayer dielectric film, forming a silicon hydronitride film on the interlayer dielectric film so as to cover the interconnection layer, forming a lower electrode on this silicon hydronitride film and forming a second contact to be connected to the interconnection layer through the silicon hydronitride film, and forming a ferroelectric layer on the lower electrode.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: May 13, 2014
    Assignee: Gold Charm Limited
    Inventor: Hiroshi Tanabe
  • Patent number: 8722572
    Abstract: A metal catalyst substrate 1 is equipped with a honeycomb body 2 in which a corrugated metal foil 4 and a flat metal foil 5 are multiply rolled, their leader portions being overlapped with each other. A restricting portion 8 is formed at a core portion 7 of the honeycomb body 2 by a portion of the core portion being deformed to restrict flow of exhaust gas in a core portion 7.
    Type: Grant
    Filed: January 12, 2010
    Date of Patent: May 13, 2014
    Assignee: Calsonic Kansei Corporation
    Inventors: Hiroshi Kodama, Kimiyoshi Nishizawa, Hiroshi Tanabe, Akio Sano, Misao Oinuma
  • Patent number: 8710507
    Abstract: A method for manufacturing a semiconductor thin film is provided which can form its crystal grains having a uniform direction of crystal growth and being large in size and a manufacturing equipment using the above method, and a method for manufacturing a thin film transistor. In the above method, by applying an energy beam partially intercepted by a light shielding element, melt and re-crystallization occur with a light-shielded region as a starting point. The irradiation of the beam gives energy to the light-shielded region of the silicon thin film so that melt and re-crystallization occur with the light-shielded region as the starting point and so that a local temperature gradient in the light-shielded region is made to be 1200° C./?m or more. In the manufacturing method, a resolution of an optical system used to apply the energy beam is preferably 4 ?m or less.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: April 29, 2014
    Assignee: Getner Foundation LLC
    Inventor: Hiroshi Tanabe
  • Publication number: 20140055722
    Abstract: To suppress light leakage at the time of dark state, and to provide a liquid crystal display device whose electrodes in the reflection areas can be formed with high precision. The liquid crystal display device has a reflection area within a pixel unit by corresponding at least to a reflection plate forming part, and the reflection area is driven with a lateral electric field mode and normally-white. A driving electrode for forming an electric field to a liquid crystal layer of the reflection area is formed on the reflection plate via an insulating film by using a non-transparent electric conductor.
    Type: Application
    Filed: June 17, 2013
    Publication date: February 27, 2014
    Inventors: Kenichi MORI, Michiaki SAKAMOTO, Ken SUMIYOSHI, Hiroshi NAGAI, Kenichirou NAKA, Masayuki JUMONJI, Hiroshi TANABE
  • Publication number: 20140020750
    Abstract: The present invention addresses the problem of providing a novel silicon substrate having a textured surface by dry-etching the surface of a silicon substrate having (111) orientation and thereby forming a texture thereon. The present invention provides a silicon substrate having (111) orientation, said silicon substrate having a textured surface that includes multiple protrusions which each comprise three slant faces and have heights of 100 to 8000 nm. This process for producing a silicon substrate includes: a step of preparing a silicon substrate having (111) orientation; and a step of blowing an etching gas onto the surface of the silicon substrate, said etching gas containing one or more gases selected from the group consisting of ClF3, XeF2, BrF3, BrF5 and NF3.
    Type: Application
    Filed: March 28, 2012
    Publication date: January 23, 2014
    Applicant: PANASONIC CORPORATION
    Inventors: Yasushi Taniguchi, Shigeru Sankawa, Kouji Arai, Hiroshi Tanabe, Ichiro Nakayama, Naoshi Yamaguchi
  • Patent number: 8628863
    Abstract: Provided is an organic light-emitting device having an optical output with high luminance and high color purity with extremely high efficiency. The organic light-emitting device includes an organic layer between the anode and the cathode, in which one of the anode and the cathode is a transparent electrode or a semi-transparent electrode and at least one layer of the organic layer contains at least one kind of indenopyrene compound having a specific structure.
    Type: Grant
    Filed: November 6, 2009
    Date of Patent: January 14, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takeshi Sekiguchi, Hiroshi Tanabe, Hiroki Ohrui, Masanori Seki
  • Patent number: 8582202
    Abstract: When it is detected that a solid immersion lens comes into contact with the semiconductor device, the lens is caused to vibrate by a vibration generator unit. Next, a reflected light image from the lens is input to calculate a reflected light quantity of the reflected light image, and it is judged whether a ratio of the reflected light quantity to an incident light quantity is not greater than a threshold value. When the ratio is greater than the threshold value, it is judged that optical close contact between the lens and the semiconductor device is not achieved, and the lens is again caused to vibrate. When the ratio is not greater than the threshold value, it is judged that optical close contact between the lens and the semiconductor device is achieved, and an observed image of the semiconductor device is acquired.
    Type: Grant
    Filed: June 13, 2008
    Date of Patent: November 12, 2013
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Hirotoshi Terada, Hiroshi Tanabe
  • Patent number: 8570455
    Abstract: A semiconductor device includes a supporting substrate; a semiconductor film on the supporting substrate; a gate insulating film on the semiconductor film; a gate electrode on the gate insulating film; and a source region and a drain region formed by introducing impurity elements to the semiconductor film. The thickness of the semiconductor film is within the range of 20 nm to 40 nm. Low-concentration regions are provided between the source region and a channel forming region, and between the drain region and the channel forming region, respectively. The low-concentration regions each have an impurity concentration smaller than that of the source region and that of the drain region, and the impurity concentration in a lower surface side region on the side of the supporting substrate is smaller than that of an upper surface side region on the opposite side.
    Type: Grant
    Filed: March 30, 2009
    Date of Patent: October 29, 2013
    Assignee: NLT Technologies, Ltd.
    Inventors: Shigeru Mori, Isao Shouji, Hiroshi Tanabe
  • Patent number: 8508852
    Abstract: To suppress bad shaping generated due to fusion of neighboring cylindrical lenses in a lens sheet formed by using an ultraviolet curable resin, for example. A lens sheet includes: a substrate formed with a transparent material; a plurality of protruded lines provided on the substrate in parallel at a specific pitch; and a plurality of cylindrical lenses, each of which is provided between the plurality of protruded lines on the substrate. The protruded line for forming the lens is designed to be constituted with a set of two lines, i.e., a left protruded line and a right protruded line, to suppress fusion of the neighboring lenses.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: August 13, 2013
    Assignee: NLT Technologies, Ltd.
    Inventors: Hiroshi Okumura, Jin Matsushima, Hiroshi Tanabe
  • Publication number: 20130183791
    Abstract: The purpose of the present invention is to obtain a finer texture for a silicon substrate having a textured surface and thereby obtain a thinner silicon substrate for a solar cell. The invention provides a silicon substrate that has a thickness of 50 [mu]m or less and substrate surface orientation (111), and that has a textured surface on which a texture has been formed. Such a silicon substrate is produced by a process comprising a step (A) for preparing a silicon substrate that preferably has a thickness of 50 [mu]m or less and substrate surface orientation (111), and a step (B) for texturing by blowing etching as comprising a fluorine-containing gas onto the surface of the prepared silicon substrate.
    Type: Application
    Filed: April 13, 2012
    Publication date: July 18, 2013
    Applicant: PANASONIC CORPORATION
    Inventors: Ichiro Nakayama, Tsuyoshi Nomura, Tomohiro Okumura, Mitsuo Saitoh, Hiroshi Tanabe, Yukiya Usui
  • Patent number: 8488087
    Abstract: To suppress light leakage at the time of dark state, and to provide a liquid crystal display device whose electrodes in the reflection areas can be formed with high precision. The liquid crystal display device has a reflection area within a pixel unit by corresponding at least to a reflection plate forming part, and the reflection area is driven with a lateral electric field mode and normally-white. A driving electrode for forming an electric field to a liquid crystal layer of the reflection area is formed on the reflection plate via an insulating film by using a non-transparent electric conductor.
    Type: Grant
    Filed: September 24, 2008
    Date of Patent: July 16, 2013
    Assignee: NLT Technologies, Ltd.
    Inventors: Kenichi Mori, Michiaki Sakamoto, Ken Sumiyoshi, Hiroshi Nagai, Kenichirou Naka, Masayuki Jumonji, Hiroshi Tanabe
  • Patent number: 8427620
    Abstract: A liquid crystal display device of IPS mode includes an array of pixels arranged in a matrix pattern by crossing a plurality of video signal lines and a plurality of scanning signal lines each other. Each of the pixels is provided with at least a switching element. A transparent insulating film is provided on both signal lines, and a plurality of pixel electrodes, common electrodes and common lines are provided on the transparent insulating film. The common lines are formed in a grid-shaped pattern such that a first group of the common lines is made of a first conductor having lower reflectivity against optical light than that of metal while a second group of the common lines is made of a second conductor including a metal layer such that the first group and the second group are crossing each other along the video signal lines and the scanning signal lines.
    Type: Grant
    Filed: February 16, 2010
    Date of Patent: April 23, 2013
    Assignee: NLT Technologies, Ltd.
    Inventors: Soichi Saito, Shinya Niioka, Masayuki Jumonji, Hiroshi Tanabe, Masamichi Shimoda
  • Publication number: 20130074176
    Abstract: In a confidential-communication system that uses a first-communication network that is Internet capable of confidential communication using VPN, and a second communication network that is an audio-circuit network, a method is implemented wherein a send/receive-processing portion 5 of a communication control device 3 completes authentication between users by implementing a P2P connection between each communication control device 3 by referencing specific information that specifies another party of a P2P connection in a memory portion 4 on the communication device 3 before confidential communication starts using VPN; a confidential-communication preparation portion 70 of the communication control device 3 exchanges via the second communication network VPN joint information required to establish a VPN link with the first communication network; and a switching portion 71 of the communication control device 3 starts confidential communication using VPN over a first-communication network.
    Type: Application
    Filed: March 11, 2011
    Publication date: March 21, 2013
    Inventors: Akira Nishihata, Hiroshi Tanabe
  • Patent number: 8389345
    Abstract: To achieve TFT having a high light-resistance characteristic with a suppressed light leak current at low cost by simplifying the manufacturing processes. The TFT basically includes: a light-shielding film formed on a glass substrate that serves as an insulating substrate; an insulating film formed on the light-shielding film; a semiconductor film formed on the insulating film; and a gate insulating film formed on the semiconductor film. Each layer of a laminate that is configured with three layers of the light-shielding film, the insulating film, and the semiconductor film is patterned simultaneously. Further, each layer of the laminate is configured with silicon or a material containing silicon.
    Type: Grant
    Filed: November 26, 2010
    Date of Patent: March 5, 2013
    Assignee: NEC LCD Technologies, Ltd.
    Inventor: Hiroshi Tanabe
  • Patent number: 8377805
    Abstract: A method for manufacturing a semiconductor thin film is provided which can form its crystal grains having a uniform direction of crystal growth and being large in size and a manufacturing equipment using the above method, and a method for manufacturing a thin film transistor. In the above method, by applying an energy beam partially intercepted by a light shielding element, melt and re-crystallization occur with a light-shielded region as a starting point. The irradiation of the beam gives energy to the light-shielded region of the silicon thin film so that melt and re-crystallization occur with the light-shielded region as the starting point and so that a local temperature gradient in the light-shielded region is made to be 1200° C./?m or more. In the manufacturing method, a resolution of an optical system used to apply the energy beam is preferably 4 ?m or less.
    Type: Grant
    Filed: January 26, 2012
    Date of Patent: February 19, 2013
    Assignee: Getner Foundation LLC
    Inventor: Hiroshi Tanabe
  • Patent number: 8334553
    Abstract: A thin-film transistor manufactured on a transparent substrate has a structure of a top gate type crystalline silicon thin-film transistor in which a light blocking film, a base layer, a crystalline silicon film, a gate insulating film, and a gate electrode film arranged not to overlap at least a channel region are sequentially formed on the transparent substrate. The channel region has channel length L, LDD regions having LDD length d on both sides of the channel region, a source region, and a drain region are formed in the crystalline silicon film. The light blocking film is divided across the channel region. Interval x between the divided light blocking films is equal to or larger than channel length L and equal to or smaller than a sum of channel length L and a double of LDD length d (L+2d), allowing low the manufacturing cost and suppressed photo leak current.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: December 18, 2012
    Assignee: NLT Technologies, Ltd.
    Inventors: Shigeru Mori, Takahiro Korenari, Hiroshi Tanabe
  • Patent number: 8330193
    Abstract: The present invention provides a high-performance silicon oxide film as a gate insulation film and a semiconductor device having superior electric characteristics. The silicon oxide film according to the present invention includes CO2 in the film, wherein, when an integrated intensity of a peak is expressed by (peak width at half height)×(peak height) in an infrared absorption spectrum, the integrated intensity of a CO2-attributed peak which appears in the vicinity of a wave number of 2,340 cm?1 is 8E-4 times or more with respect to the integrated intensity of an SiO2-attributed peak which appears in the vicinity of a wave number of 1,060 cm?1.
    Type: Grant
    Filed: June 2, 2008
    Date of Patent: December 11, 2012
    Assignee: NLT Technologies, Ltd.
    Inventors: Shigeru Mori, Hiroshi Tanabe, Jun Tanaka
  • Patent number: 8242553
    Abstract: A thin film transistor (TFT) substrate includes first and second TFTs on the same substrate. The first TFT has a feature that a lower conductive layer or a bottom gate electrode layer is provided between the substrate and a first insulating layer while an upper conductive layer or a top gate electrode layer is disposed on a second insulating layer formed on a semiconductor layer which is formed on the first insulating layer. The first conductive layer has first and second areas such that the first area overlaps with the first conductive layer without overlapping with the semiconductor layer while the second area overlaps with the semiconductor layer, and the first area is larger than the second area while the second insulating layer is thinner than the first insulating layer. The second TFT has the same configuration as the first TFT except that the gate electrode layer is eliminated.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: August 14, 2012
    Assignee: NLT Technologies, Ltd.
    Inventors: Takahiro Korenari, Hiroshi Tanabe