Patents by Inventor Hiroshige Hirano
Hiroshige Hirano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8421236Abstract: A semiconductor device includes an electrode pad formed above a semiconductor substrate, and being a connecting portion for an external electrical connection; a multilayer body including a plurality of first interconnect layers formed in a plurality of insulating films stacked between the semiconductor substrate and the connecting portion and including an upper interconnect connected to the connecting portion, and a via configured to connect the first interconnect layers; a ring body formed in the plurality of insulating films to surround the multilayer body without interposing space, and including a plurality of second interconnect layers and at least one line via linearly connecting the second interconnect layers; and a lead line electrically connecting the connecting portion to an internal circuit. The multilayer body is connected to the ring body by at least one of the plurality of first interconnect layers. The lead line is connected to the ring body.Type: GrantFiled: December 22, 2010Date of Patent: April 16, 2013Assignee: Panasonic CorporationInventors: Yukitoshi Ota, Hiroshige Hirano, Yutaka Itou
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Patent number: 8344515Abstract: A semiconductor device includes a plurality of through vias extending through a substrate. The plurality of through vias are arranged dividedly in three or more via groups. Each of the via groups includes three or more of the through vias that are arranged in two dimensions.Type: GrantFiled: May 18, 2010Date of Patent: January 1, 2013Assignee: Panasonic CorporationInventors: Taichi Nishio, Hiroshige Hirano, Yukitoshi Ota
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Patent number: 8338958Abstract: A semiconductor device includes: a semiconductor substrate having a first surface as a surface on which an element is formed, and a second surface opposite to the first surface; a through hole formed so as to extend through the semiconductor substrate from the first surface to the second surface; an insulating film formed on an inner wall of the through hole; and a conductive portion formed in a space surrounded by the insulating film in the through hole. The insulating film continuously extends on the inner wall of the through hole and on the second surface.Type: GrantFiled: July 26, 2010Date of Patent: December 25, 2012Assignee: Panasonic CorporationInventors: Taichi Nishio, Hiroshige Hirano, Yukitoshi Ota
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Publication number: 20120256322Abstract: A semiconductor device includes a first semiconductor chip provided with a first semiconductor element including a plurality of element electrodes; and a first substrate having an element mounting surface on which the first semiconductor chip is mounted. The first substrate includes a plurality of first electrodes, each formed on the element mounting surface; a plurality of first interconnects connected to the first electrodes; a plurality of second electrodes formed on a surface opposite to the element mounting surface; a plurality of second interconnects connected to the second electrodes; a plurality of through-hole interconnects penetrating the first substrate and connecting the first interconnects to the second interconnects; and a third semiconductor element. The first side of the first substrate is shorter than the first side of the first semiconductor chip.Type: ApplicationFiled: June 13, 2012Publication date: October 11, 2012Applicant: PANASONIC CORPORATIONInventors: Fumito Itou, Hiroshige Hirano, Yukitoshi Ota
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Patent number: 8237281Abstract: A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip region of the semiconductor substrate and a chip strength reinforcement provided in part of the chip region near the seal ring. The chip strength reinforcement is made of a plurality of dummy wiring structures and each of the plurality of dummy wiring structures is formed to extend across and within two or more of the wiring layers including one or none of the bottommost wiring layer and the topmost wiring layer using a via portion.Type: GrantFiled: January 4, 2011Date of Patent: August 7, 2012Assignee: Panasonic CorporationInventors: Koji Takemura, Hiroshige Hirano, Yutaka Itoh, Hikari Sano, Masao Takahashi, Koji Koike
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Publication number: 20120181670Abstract: A semiconductor device includes: an interlayer insulating film formed on a substrate; a wiring formed in the interlayer insulating film in a chip region of the substrate; a seal ring formed in the interlayer insulating film in a periphery of the chip region and continuously surrounding the chip region; and a first protective film formed on the interlayer insulating film having the wiring and the seal ring formed therein. A first opening is formed in the first protective film in a region located outside the seal ring when viewed from the chip region, and the interlayer insulating film is exposed in the first opening.Type: ApplicationFiled: March 23, 2012Publication date: July 19, 2012Applicant: Panasonic CorporationInventors: Koji TAKEMURA, Hiroshige Hirano, Yutaka Itoh, Hikari Sano, Koji Koike
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Publication number: 20120112354Abstract: A semiconductor device includes a first interconnect layer and a second interconnect layer provided above or under the first interconnect layer. The first interconnect layer includes a plurality of first interconnect blocks, and in each of the first interconnect blocks, a first interconnect has a first potential, and extends in at least two or more directions, and a second interconnect has a second potential, and extends in at least two or more directions. The second interconnect layer includes a third interconnect which electrically connects the first interconnect of one of a pair of adjacent first interconnect blocks and the first interconnect of the other of the pair of adjacent first interconnect blocks, and a fourth interconnect which electrically connects the second interconnect of one of the pair of adjacent first interconnect blocks and the second interconnect of the other of the pair of adjacent first interconnect blocks.Type: ApplicationFiled: November 4, 2011Publication date: May 10, 2012Applicant: PANASONIC CORPORATIONInventors: Hiroshige Hirano, Yukitoshi Ota
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Patent number: 8164163Abstract: A semiconductor device includes: an interlayer insulating film formed on a substrate; a wiring formed in the interlayer insulating film in a chip region of the substrate; a seal ring formed in the interlayer insulating film in a periphery of the chip region and continuously surrounding the chip region; and a first protective film formed on the interlayer insulating film having the wiring and the seal ring formed therein. A first opening is formed in the first protective film in a region located outside the seal ring when viewed from the chip region, and the interlayer insulating film is exposed in the first opening.Type: GrantFiled: February 12, 2008Date of Patent: April 24, 2012Assignee: Panasonic CorporationInventors: Koji Takemura, Hiroshige Hirano, Yutaka Itoh, Hikari Sano, Koji Koike
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Publication number: 20120080780Abstract: A semiconductor device includes: a semiconductor substrate; a first interlayer insulating film formed over the semiconductor substrate; a pad formed above the first interlayer insulating film; and a plurality of first interconnects spaced apart from each other in a portion of the first interlayer insulating film located below the pad. Below the pad, the first interconnects are formed in quadrangular plan shapes.Type: ApplicationFiled: December 12, 2011Publication date: April 5, 2012Applicant: Panasonic CorporationInventors: Koji TAKEMURA, Hiroshige Hirano, Masao Takahashi, Hikari Sano, Yutaka Itoh, Koji Koike
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Publication number: 20120025394Abstract: A semiconductor device includes: a first insulating film formed on a substrate; a pad embedded in the first insulating film; and a second insulating film that is formed on the first insulating film and has an opening exposing at least part of the pad. The pad includes a plurality of pad interconnects, and an interconnect link is provided to electrically connect adjacent interconnects among the plurality of pad interconnects. The width of the pad interconnects is smaller than the height of the pad interconnects and larger than the width of the interconnect link.Type: ApplicationFiled: July 27, 2011Publication date: February 2, 2012Inventors: Hiroshige Hirano, Yukitoshi Ota, Yutaka Itoh
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Patent number: 8102056Abstract: A semiconductor device includes: a semiconductor substrate; a first interlayer insulating film formed over the semiconductor substrate; a pad formed above the first interlayer insulating film; and a plurality of first interconnects spaced apart from each other in a portion of the first interlayer insulating film located below the pad. Below the pad, the first interconnects are formed in quadrangular plan shapes.Type: GrantFiled: August 29, 2006Date of Patent: January 24, 2012Assignee: Panasonic CorporationInventors: Koji Takemura, Hiroshige Hirano, Masao Takahashi, Hikari Sano, Yutaka Itoh, Koji Koike
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Patent number: 8044482Abstract: A semiconductor device includes an insulating film formed on a semiconductor substrate, a contact wiring formed in the insulating film, a protective film formed on the contact wiring and the insulating film, an opening portion formed in the protective film, the contact wiring being exposed through the opening portion, and an electrode pad formed in the opening portion, the electrode pad being electrically connected to the contact wiring. A region where the contact wiring is not provided is present below the opening portion.Type: GrantFiled: August 12, 2009Date of Patent: October 25, 2011Assignee: Panasonic CorporationInventors: Yukitoshi Ota, Hiroshige Hirano, Yutaka Itou, Koji Koike
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Publication number: 20110175232Abstract: A semiconductor device includes an electrode pad formed above a semiconductor substrate, and being a connecting portion for an external electrical connection; a multilayer body including a plurality of first interconnect layers formed in a plurality of insulating films stacked between the semiconductor substrate and the connecting portion and including an upper interconnect connected to the connecting portion, and a via configured to connect the first interconnect layers; a ring body formed in the plurality of insulating films to surround the multilayer body without interposing space, and including a plurality of second interconnect layers and at least one line via linearly connecting the second interconnect layers; and a lead line electrically connecting the connecting portion to an internal circuit. The multilayer body is connected to the ring body by at least one of the plurality of first interconnect layers. The lead line is connected to the ring body.Type: ApplicationFiled: December 22, 2010Publication date: July 21, 2011Inventors: Yukitoshi OTA, Hiroshige Hirano, Yutaka Itou
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Publication number: 20110095430Abstract: A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip region of the semiconductor substrate and a chip strength reinforcement provided in part of the chip region near the seal ring. The chip strength reinforcement is made of a plurality of dummy wiring structures and each of the plurality of dummy wiring structures is formed to extend across and within two or more of the wiring layers including one or none of the bottommost wiring layer and the topmost wiring layer using a via portion.Type: ApplicationFiled: January 4, 2011Publication date: April 28, 2011Applicant: PANASONIC CORPORATIONInventors: Koji TAKEMURA, Hiroshige Hirano, Yutaka Itoh, Hikari Sano, Masao Takahashi, Koji Koike
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Patent number: 7888801Abstract: A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip region of the semiconductor substrate and a chip strength reinforcement provided in part of the chip region near the seal ring. The chip strength reinforcement is made of a plurality of dummy wiring structures and each of the plurality of dummy wiring structures is formed to extend across and within two or more of the wiring layers including one or none of the bottommost wiring layer and the topmost wiring layer using a via portion.Type: GrantFiled: April 27, 2009Date of Patent: February 15, 2011Assignee: Panasonic CorporationInventors: Koji Takemura, Hiroshige Hirano, Yutaka Itoh, Hikari Sano, Masao Takahashi, Koji Koike
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Publication number: 20100289151Abstract: A semiconductor device includes a lower-layer wire, an upper-layer wire including a wire portion and a first wide portion whose wire width is greater than the wire portion, and a contact formation portion in which a contact portion for connecting the lower-layer wire and the first wide portion with each other is provided. The contact formation portion has a planar shape of which a length L1 in a direction parallel to a wire width direction of the first wide portion is greater than a length L2 in a direction parallel to a wire length direction of the first wide portion.Type: ApplicationFiled: April 2, 2010Publication date: November 18, 2010Inventors: Chikako CHIDA, Fumito Itou, Hiroshige Hirano
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Publication number: 20100283130Abstract: A semiconductor device includes: a semiconductor substrate having a first surface as a surface on which an element is formed, and a second surface opposite to the first surface; a through hole formed so as to extend through the semiconductor substrate from the first surface to the second surface; an insulating film formed on an inner wall of the through hole; and a conductive portion formed in a space surrounded by the insulating film in the through hole. The insulating film continuously extends on the inner wall of the through hole and on the second surface.Type: ApplicationFiled: July 26, 2010Publication date: November 11, 2010Applicant: PANASONIC CORPORATIONInventors: Taichi NISHIO, Hiroshige Hirano, Yukitoshi Ota
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Publication number: 20100225005Abstract: A semiconductor device includes a plurality of through vias extending through a substrate. The plurality of through vias are arranged dividedly in three or more via groups. Each of the via groups includes three or more of the through vias that are arranged in two dimensions.Type: ApplicationFiled: May 18, 2010Publication date: September 9, 2010Applicant: PANASONIC CORPORATIONInventors: Taichi NISHIO, Hiroshige Hirano, Yukitoshi Ota
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Publication number: 20100090344Abstract: A semiconductor device includes an insulating film formed on a semiconductor substrate, a contact wiring formed in the insulating film, a protective film formed on the contact wiring and the insulating film, an opening portion formed in the protective film, the contact wiring being exposed through the opening portion, and an electrode pad formed in the opening portion, the electrode pad being electrically connected to the contact wiring. A region where the contact wiring is not provided is present below the opening portion.Type: ApplicationFiled: August 12, 2009Publication date: April 15, 2010Inventors: Yukitoshi Ota, Hiroshige Hirano, Yutaka Itou, Koji Koike
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Patent number: RE41879Abstract: Provided is a semiconductor memory device compatible with a SRAM and capable of a high-speed data transfer operation while maintaining data reliability. An access to a memory core 6 starts when an external chip enable signal XCE performs a falling transition. Simultaneously, an external write enable signal XWE and an external address signal ADD are received, and a memory cell 1, in the memory core 6, corresponding to the received external address signal ADD is selected. When a data read-out from the memory cell 1 or a data write-in to the memory cell 1 is complete, a rewrite timer 7 is activated in accordance with a rising transition of an external chip enable signal XCE or a rising transition of the external write enable signal XWE for performing a data rewrite for the memory cell 1.Type: GrantFiled: June 3, 2008Date of Patent: October 26, 2010Assignee: Panasonic CorporationInventors: Shunichi Iwanari, Masahiko Sakagami, Hiroshige Hirano, Tetsuji Nakakuma, Takashi Miki, Yasushi Gohou, Kunisato Yamaoka, Yasuo Murakuki