Abstract: A semiconductor device includes: a circuit region having a function element formed on a semiconductor substrate; a scribe region located between the circuit region and another circuit region formed spaced from the circuit region, the scribe region including a cutting region and non-cutting regions provided at both sides of the cutting region; a first interlayer insulating film formed in the scribe region on the semiconductor substrate; a first dummy pattern made of conductive material and formed in the first interlayer insulating film in the cutting region; and a second dummy pattern made of conductive material and formed in the first interlayer insulating film in each of the non-cutting regions. The ratio, per unit area, of the area of the first dummy pattern to the area of the cutting region is lower than the ratio, per unit area, of the area of the second dummy pattern to the area of the non-cutting regions.

Abstract: A ferroelectric memory device having plural memory cells, each composed of a memory cell transistor and a memory cell capacitor including a lower electrode that is independent for each memory cell capacitor, a ferroelectric layer formed on the lower electrode, and an upper electrode layer formed on the ferroelectric layer. A plurality of the upper electrode layers are connected together and constitute a plate electrode, and the width of the upper electrode is narrower than the width of the ferroelectric layer. Accordingly, by making the width of the upper electrode narrower than the width of the ferroelectric layer, it is possible to prevent current leakage between the upper electrode and the lower electrode, which reduces the placement interval of the memory cell capacitors without causing current leakage between the upper electrode and the lower electrode, and results in a smaller memory cell size.

Abstract: A ferroelectric memory device having plural memory cells, each composed of a memory cell transistor and a memory cell capacitor including a lower electrode that is independent for each memory cell capacitor, a ferroelectric layer formed on the lower electrode, and an upper electrode layer formed on the ferroelectric layer. A plurality of the upper electrode layers are connected together and constitute a plate electrode, and the width of the upper electrode is narrower than the width of the ferroelectric layer. Accordingly, by making the width of the upper electrode narrower than the width of the ferroelectric layer, it is possible to prevent current leakage between the upper electrode and the lower electrode, which reduces the placement interval of the memory cell capacitors without causing current leakage between the upper electrode and the lower electrode, and results in a smaller memory cell size.

Abstract: A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip region of the semiconductor substrate and a chip strength reinforcement provided in part of the chip region near the seal ring. The chip strength reinforcement is made of a plurality of dummy wiring structures and each of the plurality of dummy wiring structures is formed to extend across and within two or more of the wiring layers including one or none of the bottommost wiring layer and the topmost wiring layer using a via portion.

Abstract: A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip region of the semiconductor substrate and a chip strength reinforcement provided in part of the chip region near the seal ring. The chip strength reinforcement is made of a plurality of dummy wiring structures and each of the plurality of dummy wiring structures is formed to extend across and within two or more of the wiring layers including one or none of the bottommost wiring layer and the topmost wiring layer using a via portion.

Abstract: A Ti barrier film and a TiN barrier film are formed between a top-level pad made of copper or an alloy film mainly composed of copper and an Al pad. The Ti barrier film is formed to have a greater thickness than the TiN barrier film.

Abstract: The semiconductor integrated circuit includes: a first wiring layer including a plurality of first interconnects formed to run in a first direction; a second wiring layer formed above the first wiring layer, the second wiring layer including a plurality of second interconnects formed to run in a second direction vertical to the first direction; and a third wiring layer formed above the second wiring layer, the third wiring layer including a plurality of third interconnects formed to run in the same direction as the second direction.

Abstract: In order to omit a reset transistor between a storage node and a cell plate line of a memory cell, a cell plate line is fixed to a potential substantially equal to a ground potential and a bit line is driven with positive and negative voltages.

Abstract: A semiconductor device includes: an interlayer insulating film formed on a substrate; a wiring formed in the interlayer insulating film in a chip region of the substrate; a seal ring formed in the interlayer insulating film in a periphery of the chip region and continuously surrounding the chip region; and a first protective film formed on the interlayer insulating film having the wiring and the seal ring formed therein. A first opening is formed in the first protective film in a region located outside the seal ring when viewed from the chip region, and the interlayer insulating film is exposed in the first opening.

Abstract: A voltage level conversion circuit is provided with a level converter for converting a VDD1 system input signal into a VDD2 system signal, and a NOT circuit for inverting the level-converted input signal and outputting the inverted signal, and the outputs of VDD1 system NOT circuits constituting the level converter are input to only high breakdown voltage transistors in the level converter while a signal having a logical voltage level corresponding to the low power supply voltage VDD2 is input to low breakdown voltage transistors, and further, only the input signal level-converted by the level converter is input to the NOT circuit.

Abstract: A semiconductor device includes: a circuit region having a function element formed on a semiconductor substrate; a scribe region located between the circuit region and another circuit region formed spaced from the circuit region, the scribe region including a cutting region and non-cutting regions provided at both sides of the cutting region; a first interlayer insulating film formed in the scribe region on the semiconductor substrate; a first dummy pattern made of conductive material and formed in the first interlayer insulating film in the cutting region; and a second dummy pattern made of conductive material and formed in the first interlayer insulating film in each of the non-cutting regions. The ratio, per unit area, of the area of the first dummy pattern to the area of the cutting region is lower than the ratio, per unit area, of the area of the second dummy pattern to the area of the non-cutting regions.

Abstract: A ferroelectric memory of the present invention comprises: a plurality of normal cells, each of which includes a first ferroelectric capacitor for holding data and a first transistor connected to a first electrode of the first ferroelectric capacitor; a first bit line connected to the first transistor; a first bit line precharge circuit which is a switch circuit provided between the first bit line and a ground; and a word line connected to a gate of the first transistor. The word line is deactivated to disconnect the first ferroelectric capacitor from the first bit line before the first bit line precharge circuit is driven to discharge a potential of the first bit line.

Abstract: Provided is a semiconductor memory device compatible with a SRAM and capable of a high-speed data transfer operation while maintaining data reliability. An access to a memory core 6 starts when an external chip enable signal XCE performs a falling transition. Simultaneously, an external write enable signal XWE and an external address signal ADD are received, and a memory cell 1, in the memory core 6, corresponding to the received external address signal ADD is selected. When a data read-out from the memory cell 1 or a data write-in to the memory cell 1 is complete, a rewrite timer 7 is activated in accordance with a rising transition of an external chip enable signal XCE or a rising transition of the external write enable signal XWE for performing a data rewrite for the memory cell 1.

Abstract: A voltage level conversion circuit for converting a voltage level of a low voltage system input signal into a voltage level of a high voltage system signal comprises a latch circuit comprising plural high-breakdown-voltage MOS transistors having a high power supply voltage as a breakdown voltage, a first high-breakdown-voltage N channel MOS transistor which discharges one of the latch nodes of the latch circuit, and a second high-breakdown-voltage N channel MOS transistor which discharges the other latch node, and a pulse signal obtained by boosting a low voltage system pulse signal is applied to a gate of the first or second high-breakdown voltage N channel MOS transistor when the input signal transits.

Abstract: A Ti barrier film and a TiN barrier film are formed between a top-level pad made of copper or an alloy film mainly composed of copper and an Al pad. The Ti barrier film is formed to have a greater thickness than the TiN barrier film.

Abstract: A semiconductor device includes: a semiconductor substrate; a first interlayer insulating film formed over the semiconductor substrate; a pad formed above the first interlayer insulating film; and a plurality of first interconnects spaced apart from each other in a portion of the first interlayer insulating film located below the pad. Below the pad, the first interconnects are formed in quadrangular plan shapes.

Abstract: A semiconductor device includes a differential sense amplifier connected to a bit line, and a data transfer circuit including a column selection switch for turning ON/OFF the connection between a data line and the bit line. The semiconductor device incorporates one of the following features: the on-state resistance of the column selection switch being higher than that of a transistor array of the differential sense amplifier; separate provision of two column selection switches, one for read operation and the other for write operation; provision of a bit line additional capacitance and a connection control switch therefor; and provision of a data line dividing switch.

Abstract: A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip region of the semiconductor substrate and a chip strength reinforcement provided in part of the chip region near the seal ring. The chip strength reinforcement is made of a plurality of dummy wiring structures and each of the plurality of dummy wiring structures is formed to extend across and within two or more of the wiring layers including one or none of the bottommost wiring layer and the topmost wiring layer using a via portion.

Abstract: In order to omit a reset transistor between a storage node and a cell plate line of a memory cell, a cell plate line is fixed to a potential substantially equal to a ground potential and a bit line is driven with positive and negative voltages.

Abstract: To provide a semiconductor storage device which can adapt to assembly processes involving different treatment temperatures, can become unrewritable when rewriting of data by the user is prohibited, negates the necessity for developing different semiconductor storage devices, and lowers development cost. A semiconductor storage device is provided with, as areas for storing faulty address information indicating a faulty area and operation mode setting information about the semiconductor storage device, a first setting function storage area 103 formed from electrically-rewritable nonvolatile memory and a second setting function storage area 102 formed from once-rewritable nonvolatile memory. Transfer of faulty address information to a faulty address register 111 and transfer of operation mode setting information to an operation mode register 110 are selectively performed.