Abstract: The present invention provides a ferroelectric memory device (101) having plural memory cells each composed of a memory cell transistor and a memory cell capacitor, in which the respective memory cell capacitor (101a) comprises a lower electrode (2) that is independent for each of the memory cell capacitors, a ferroelectric layer (3) that is formed on the lower electrode (2), and an upper electrode layer (4) which is formed on the ferroelectric layer (3), and a plurality of the upper electrode layers are connected together and constitute a plate electrode, and the width of the upper electrode is narrower than the width of the ferroelectric layer.

Abstract: A semiconductor memory device includes memory cell blocks (11) through (14) including a nonvolatile memory cell. The memory cell blocks (11) through (14) include chip-data storing regions (11b) through (14b) for storing chip data containing operation parameters of the semiconductor memory device and pass-flag storing regions (11c) through (14c) for storing pass flags which correspond to the respective chip-data storing regions and show the validity of the stored chip data. The chip-data storing regions store the same chip data.

Abstract: A semiconductor device includes a differential sense amplifier connected to a bit line, and a data transfer circuit including a column selection switch for turning ON/OFF the connection between a data line and the bit line. The semiconductor device incorporates one of the following features: the on-state resistance of the column selection switch being higher than that of a transistor array of the differential sense amplifier; separate provision of two column selection switches, one for read operation and the other for write operation; provision of a bit line additional capacitance and a connection control switch therefor; and provision of a data line dividing switch.

Abstract: In a ferro-electric memory including reference cells, if one reference cell is associated with a plurality of normal cells, a period in which “L” data is written in the reference cell and a period in which “H” data is written or read out in/from the reference cell are controlled to be shorter than a period in which “L” data is written in each normal cell and a period in which “H” data is written or read out in/from each normal cell, respectively. In this manner, stress applied to the reference cell is reduced and, even if writing or reading is repeatedly performed on the normal cells, the reliability of the reference cell is enhanced and deterioration in characteristics of the reference cell due to repetitive rewriting of data is suppressed.

Abstract: Provided is a semiconductor memory device compatible with a SRAM and capable of a high-speed data transfer operation while maintaining data reliability. An access to a memory core 6 starts when an external chip enable signal XCE performs a falling transition. Simultaneously, an external write enable signal XWE and an external address signal ADD are received, and a memory cell 1, in the memory core 6, corresponding to the received external address signal ADD is selected. When a data read-out from the memory cell 1 or a data write-in to the memory cell 1 is complete, a rewrite timer 7 is activated in accordance with a rising transition of an external chip enable signal XCE or a rising transition of the external write enable signal XWE for performing a data rewrite for the memory cell 1.

Abstract: A voltage level conversion circuit for converting a voltage level of a low voltage system input signal into a voltage level of a high voltage system signal comprises a latch circuit comprising plural high-breakdown-voltage MOS transistors having a high power supply voltage as a breakdown voltage, a first high-breakdown-voltage N channel MOS transistor which discharges one of latch nodes of the latch circuit, and a second high-breakdown-voltage N channel MOS transistor which discharges the other latch node, and a pulse signal obtained by boosting a low voltage system pulse signal is applied to a gate of the first or second high-breakdown voltage N channel MOS transistor when the input signal transits.

Abstract: A semiconductor memory device having a memory cell array in which plural memory transistors and plural memory call capacitors, which are components of memory cells, are arranged, comprises a first wiring layer formed on the memory cell array, and a second wiring layer formed above the first wiring layer, wherein a wiring density of the first wiring layer on the memory cell array is higher than a wiring density of the second wiring layer on the memory cell array. Therefore, a hydrogen barrier property for the capacitors is improved, and an adverse effect due to stress applied to the capacitors is reduced, thereby suppressing deterioration of capacitor characteristics.

Abstract: A semiconductor device includes a differential sense amplifier connected to a bit line, and a data transfer circuit including a column selection switch for turning ON/OFF the connection between a data line and the bit line. The semiconductor device incorporates one of the following features: the on-state resistance of the column selection switch being higher than that of a transistor array of the differential sense amplifier; separate provision of two column selection switches, one for read operation and the other for write operation; provision of a bit line additional capacitance and a connection control switch therefor; and provision of a data line dividing switch.

Abstract: A semiconductor device includes a differential sense amplifier connected to a bit line, and a data transfer circuit including a column selection switch for turning ON/OFF the connection between a data line and the bit line. The semiconductor device incorporates one of the following features: the on-state resistance of the column selection switch being higher than that of a transistor array of the differential sense amplifier; separate provision of two column selection switches, one for read operation and the other for write operation; provision of a bit line additional capacitance and a connection control switch therefor; and provision of a data line dividing switch.

Abstract: To provide a semiconductor storage device which can adapt to assembly processes involving different treatment temperatures, can become unrewritable when rewriting of data by the user is prohibited, negates the necessity for developing different semiconductor storage devices, and lowers development cost. A semiconductor storage device is provided with, as areas for storing faulty address information indicating a faulty area and operation mode setting information about the semiconductor storage device, a first setting function storage area 103 formed from electrically-rewritable nonvolatile memory and a second setting function storage area 102 formed from once-rewritable nonvolatile memory. Transfer of faulty address information to a faulty address register 111 and transfer of operation mode setting information to an operation mode register 110 are selectively performed.

Abstract: A ferroelectric memory of the present invention comprises: a plurality of normal cells, each of which includes a first ferroelectric capacitor for holding data and a first transistor connected to a first electrode of the first ferroelectric capacitor; a first bit line connected to the first transistor; a first bit line precharge circuit which is a switch circuit provided between the first bit line and a ground; and a word line connected to a gate of the first transistor. The word line is deactivated to disconnect the first ferroelectric capacitor from the first bit line before the first bit line precharge circuit is driven to discharge a potential of the first bit line.

Abstract: A voltage level conversion circuit 101 is provided with a level converter 101a for converting a VDD1 system input signal into a VDD2 system signal, and a NOT circuit 30 for inverting the level-converted input signal and outputting the inverted signal, and the outputs of VDD1 system NOT circuits 21a and 21b constituting the level converter 101a are input to only high breakdown voltage transistors Qhn1 and Qhn2 in the level converter 101a while a signal having a logical voltage level corresponding to the low power supply voltage VDD2 is input to low breakdown voltage transistors Qlp1 and Qlp2, and further, only the input signal level-converted by the level converter 101a is input to the NOT circuit 30.

Abstract: A semiconductor memory device includes memory cell blocks (11) through (14) including a nonvolatile memory cell. The memory cell blocks (11) through (14) include chip-data storing regions (11b) through (14b) for storing chip data containing operation parameters of the semiconductor memory device and pass-flag storing regions (11c) through (14c) for storing pass flags which correspond to the respective chip-data storing regions and show the validity of the stored chip data. The chip-data storing regions store the same chip data.

Abstract: In a ferro-electric memory including reference cells, if one reference cell is associated with a plurality of normal cells, a period in which “L” data is written in the reference cell and a period in which “H” data is written or read out in/from the reference cell are controlled to be shorter than a period in which “L” data is written in each normal cell and a period in which “H” data is written or read out in/from each normal cell, respectively. In this manner, stress applied to the reference cell is reduced and, even if writing or reading is repeatedly performed on the normal cells, the reliability of the reference cell is enhanced and deterioration in characteristics of the reference cell due to repetitive rewriting of data is suppressed.

Abstract: A semiconductor device includes a differential sense amplifier connected to a bit line, and a data transfer circuit including a column selection switch for turning ON/OFF the connection between a data line and the bit line. The semiconductor device incorporates one of the following features: the on-state resistance of the column selection switch being higher than that of a transistor array of the differential sense amplifier; separate provision of two column selection switches, one for read operation and the other for write operation; provision of a bit line additional capacitance and a connection control switch therefor; and provision of a data line dividing switch.

Abstract: A ferroelectric memory device includes a plurality of bit line pairs, a plurality of sense amplifiers, a plurality of memory cells, a plurality of reference cells, and a control circuit. Each of the bit line pairs is composed of first and second bit lines. Each of the sense amplifiers amplifies a potential difference across the corresponding bit line pair. The memory cells are provided for the respective bit line pairs and each composed of a transistor and a ferroelectric capacitor. The reference cells are provided for the respective bit line pairs and each composed of a transistor and a ferroelectric capacitor. In addition, each of the reference cells on each of the bit line pairs retains data different from data of a reference cell on the adjacent bit line pair. The control circuit drives the sense amplifiers, the memory cells, and the reference cells. During the drive of the sense amplifier, the control circuit inactivates a reference word line connected to the reference cell.

Abstract: An electrode forming method includes the steps of: forming a conductive film on a substrate; forming, on the conductive film, a first mask pattern extending in a first direction; forming a conductive film pattern by etching the conductive film using the first mask pattern; removing the first mask pattern existing on the conductive film pattern; forming, on the substrate and on the conductive film pattern, a second mask pattern extending in a second direction different from the first direction; and forming an electrode by etching the conductive film pattern using the second mask pattern.

Abstract: A semiconductor device includes a differential sense amplifier connected to a bit line, and a data transfer circuit including a column selection switch for turning ON/OFF the connection between a data line and the bit line. The semiconductor device incorporates one of the following features: the on-state resistance of the column selection switch being higher than that of a transistor array of the differential sense amplifier; separate provision of two column selection switches, one for read operation and the other for write operation; provision of a bit line additional capacitance and a connection control switch therefor; and provision of a data line dividing switch.

Abstract: The present invention comprises a first MOS transistor whose gate and drain are connected with a first node, a second MOS transistor whose gate and drain are connected with the first node and a third node, respectively, a first resistive element which is connected between the first node and a second node, a second resistive element which is connected between the second node and a ground voltage terminal, a first NOT circuit whose input terminal is connected with the second node, whose output terminal is a fourth node, and which is connected between the third node and the ground voltage terminal, and a second NOT circuit whose input terminal is connected with the fourth node and whose output terminal is a fifth node. Consequently, the present invention can detect voltage in a stable condition with low power consumption.

Abstract: A memory cell transistor using a word line WL as the gate thereof is provided in an active region OD, and a ferroelectric capacitor, including bottom electrode, ferroelectric film and top electrode TE, is formed on a field oxide film. A first interconnection layer is made up of storage lines, each connecting the top electrode TE to one of doped layers of the memory cell transistor, and bit lines, each of which is connected to the other doped layer. In a planar layout, the storage line-intersects only one side of the top electrode TE and the bit line BL does not overlap with the top electrode TE. Thus, it is possible to prevent the retention characteristics of the ferroelectric capacitor from being deteriorated due to the stress applied by the first interconnection layer to the ferroelectric capacitor. As a result, the reliability of a ferroelectric memory device, including, in a memory cell, a ferroelectric capacitor with a ferroelectric film interposed between the bottom and top electrodes, can be improved.